ml7074a-004 Oki Semiconductor, ml7074a-004 Datasheet - Page 21

• Manufacturer Part Number: ml7074a-004
• Description: Voip Codec
• Manufacturer: Oki Semiconductor

• FR0B (In frame mode, CR11-B7 = “0”)
• DMARQ0B (In DMA mode, CR11-B7 = “1”)
• FR1B (In frame mode, CR11-B7 = “0”)
• DMARQ1B (In DMA mode, CR11-B7 = “1”)
This is the DMA acknowledgement input pin for the DMARQ0B signal during DMA access of the transmit buffer
Tie this pin to “1” when using this LSI in the frame access mode (CR11-B7 = “0”).
This is the DMA acknowledgement input pin for the DMARQ1B signal during DMA access of the receive buffer
Tie this pin to “1” when using this LSI in the frame access mode (CR11-B7 = “0”).
These are general-purpose input pins. The state (“1” or “0”) of each of these GPI0 and GPI1 pins can be read out
These are general-purpose output pins. The values set in CR17-B0 and CR17-B1 are output at these pins GPO0
and becomes valid in the DMA mode (CR11-B7 = “1”).
and becomes valid in the DMA mode (CR11-B7 = “1”).
respectively from CR16-B0 and CR16-B1. Further, GPI0 becomes the input pin for the dial pulse detector
(DPDET) in the secondary functions.
and GPO1, respectively. Further, GPO0 becomes the output pin for the dial pulse generator (DPGEN) in the
secondary functions.
FR0B (DMARQ0B)
FR1B (DMARQ1B)
ACK0B
ACK1B
GPI0, GPI1
GPO0, GPO1
OKI Semiconductor
This is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame
access. This pin outputs an “L” level when the transmit buffer becomes full, and maintains that “L” level output
until a specific number of words are read out from the MCU.
This is the DMA request output pin which outputs the signal when the transmit buffer is full during DMA access.
This output becomes “L” when the transmit buffer becomes full, and returns to the “H” level automatically on
the falling edge of the read enable signal (RDB = “1” → “0”) when there is an acknowledgement signal (ACK0B
= “0”) from the MCU. This relationship is repeated until a specific number of words are read out from the MCU.
This is the receive frame output pin which outputs the signal when the receive buffer is empty during frame
access. This pin outputs an “L” level when the receive buffer becomes empty, and maintains that “L” level
output until a specific number of words are written from the MCU.
This is the DMA request output pin which outputs the signal when the receive buffer is empty during DMA
access. This output becomes “L” when the receive buffer becomes empty, and returns to the “H” level
automatically on the falling edge of the write enable signal (WRB = “1” → “0”) when there is an
acknowledgement signal (ACK1B = “0”) from the MCU. This relationship is repeated until a specific number of
words are written from the MCU.
FEDL7074-003DIGEST-01
ML7074-004GA
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