ispgal22lv10 Lattice Semiconductor Corp., ispgal22lv10 Datasheet - Page 10

• Manufacturer Part Number: ispgal22lv10
• Description: In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

An electronic signature (ES) is provided in every ispGAL22LV10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when com-
piling a set of logic equations. In addition, many device
programmers have two separate selections for the device,
typically an ispGAL22LV10 and a ispGAL22LV10-UES (UES =
User Electronic Signature) or ispGAL22LV10-ES. This allows
users to maintain compatibility with existing 22V10 designs,
while still having the option to use the GAL device's extra feature.
The JEDEC map for the ispGAL22LV10 contains the 64 extra
fuses for the electronic signature, for a total of 5892 fuses.
However, the ispGAL22LV10 device can still be programmed
with a standard 22V10 JEDEC map (5828 fuses) with any
qualified device programmer.
A security cell is provided in every ispGAL22LV10 device to
prevent unauthorized copying of the array patterns.
programmed, this cell prevents further read access to the func-
tional bits in the device.
re-programming the device, so the original configuration can
never be examined once this cell is programmed. The Electronic
Signature is always available to the user, regardless of the state
of this control cell.
ispGAL22LV10 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch.
The ispGAL22LV10 device uses a standard 22V10 JEDEC
fusemap file to describe the device programming information.
Any third party logic compiler can produce the JEDEC file for this
device.
The ispGAL22LV10 device features In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E
when the power is turned off.
Electronic Signature
Security Cell
Latch-Up Protection
Device Programming
In-System Programmability
2
CMOS cells will not lose the pattern even
This cell can only be erased by
Once
10
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the pro-
gramming. The interface signals are Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS)
control. For details on the operation of the internal state machine
and programming of ispGAL22LV10 devices please refer to the
ISP Architecture and Programming section in this Data Book.
When testing state machine designs, all possible states and
state transitions must be verified in the design, not just those
required in the normal machine operations. This is because
certain events may occur during system operation that throw the
logic into an illegal state (power-up, line voltage glitches, brown-
outs, etc.). To test a design for proper treatment of these
conditions, a way must be provided to break the feedback paths,
and force any desired (i.e., illegal) state into the registers. Then
the machine can be sequenced and the outputs tested for correct
next state conditions.
The ispGAL22LV10 device includes circuitry that allows each
registered output to be synchronously set either high or low.
Thus, any present state condition can be forced for test sequenc-
ing. If necessary, approved GAL programmers capable of
executing test vectors perform output register preload automati-
cally.
ispGAL22LV10 devices are designed with TTL level compatible
input buffers.
impedance, and present a much lighter load to the driving logic
than bipolar TTL devices.
All input and I/O pins also have built-in active pull-ups. As a
result, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schemat-
ics on the following page.)
Specifications ispGAL22LV10
Output Register Preload
Input Buffers
-10.00
-20.00
-30.00
-40.00
-50.00
0.00
0.00
These buffers have a characteristically high
Typical Input Current
1.00
Input Voltage (Volts)
2.00
3.00
4.00