ispgdx80va Lattice Semiconductor Corp., ispgdx80va Datasheet - Page 13
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ispgdx80va
Manufacturer Part Number
ispgdx80va
Description
In-system Programmable 3.3v Generic Digital Crosspoint
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.ISPGDX80VA.pdf
(24 pages)
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101
ispGDX80VA timings are specified with a GRP load
(fanout) of four I/O cells. The figure below shows the ∆
GRP Delay with increased GRP loads. These deltas
External Timing Parameters (Continued)
ispGDX80VA Maximum
10
8
6
4
2
0
4
10
20
∆
I/O Cell Fanout
GRP Delay vs. I/O Cell Fanout
13
30
apply to any signal path traversing the GRP (MUXA-D,
OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
which do not use the GRP have no fanout delay adder.
Specifications ispGDX80VA
40
50
60
70