ispgdx160va Lattice Semiconductor Corp., ispgdx160va Datasheet - Page 11

• Manufacturer Part Number: ispgdx160va
• Description: In-system Programmable 3.3v Generic Digital Crosspoint
• Manufacturer: Lattice Semiconductor Corp.

1. All timings measured with one output switching, fast output slew rate setting, except
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
External Timing Parameters
t
t
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PARAMETER
pd
sel
max (Tog.)
max (Ext.)
su1
su2
su3
su4
suce1
suce2
suce3
h1
h2
h3
h4
hce1
hce2
hce3
gco1
gco2
co1
co2
en
dis
toeen
toedis
wh
wl
rst
rw
sl
sk
used as I/O voltage reference.
2
2
2
2
2
2
2
2
2
2
COND.
TEST
C
C
D
A
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
A
A
A
B
B
–
–
–
–
A
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
#
1
2
3
4
5
6
7
8
9
Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
Clock Frequency, Max. Toggle
Clock Frequency with External Feedback
Input Latch or Register Setup Time Before Y
Input Latch or Register Setup Time Before I/O Clock
Output Latch or Register Setup Time Before Y
Output Latch or Register Setup Time Before I/O Clock
Global Clock Enable Setup Time Before Y
Global Clock Enable Setup Time Before I/O Clock
I/O Clock Enable Setup Time Before Y
Input Latch or Reg. Hold Time (Y
Input Latch or Reg. Hold Time (I/O Clock)
Output Latch or Reg. Hold Time (Y
Output Latch or Reg. Hold Time (I/O Clock)
Global Clock Enable Hold Time (Y
Global Clock Enable Hold Time (I/O Clock)
I/O Clock Enable Hold Time (Y
Output Latch or Reg. Clock (from Y
Input Latch or Register Clock (from Y
Output Latch or Register Clock (from I/O pin) to Output Delay
Input Latch or Register Clock (from I/O pin) to Output Delay
Input to Output Enable
Input to Output Disable
Test OE Output Enable
Test OE Output Disable
Clock Pulse Duration, High
Clock Pulse Duration, Low
Register Reset Delay from RESET Low
Reset Pulse Width
Output Delay Adder for Output Timings Using Slow Slew Rate
Output Skew (tgco1 Across Chip)
Over Recommended Operating Conditions
DESCRIPTION
x
)
x
)
x
x
x
)
) to Output Delay
)
x
11
) to Output Delay
x
(
Specifications ispGDX160VA
x
tsu3+tgco1
x
x
1
)
t
sl
.
166.7
MIN. MAX.
250
3.0
2.5
2.5
2.0
2.5
1.5
3.0
0.0
0.5
0.0
1.0
0.0
1.0
0.0
2.0
2.0
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
-3
3.5
3.5
3.5
6.0
4.0
7.0
5.0
5.0
6.0
6.0
8.0
3.5
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MIN. MAX.
10.0
143
111
4.0
3.0
4.0
3.0
2.5
1.5
4.5
0.0
1.5
0.0
1.5
0.0
1.5
0.0
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
-5
14.0
5.0
5.0
5.0
8.5
6.0
9.5
6.0
6.0
6.0
6.0
5.0
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns