73k222al ETC-unknow, 73k222al Datasheet - Page 5

• Manufacturer Part Number: 73k222al
• Description: V.22, V.21, Bell 212a, Single-chip Modem
• Manufacturer: ETC-unknow

PARALLEL MICROPROCESSOR INTERFACE
NAME
WR
SERIAL MICROPROCESSOR INTERFACE
A0-A2
DATA
RD
WR
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes
DATA and AD0, AD1 and AD2 become the address only. See timing diagrams on page 20.
28-PIN
13
-
-
-
-
TYPE
I/O
I
I
I
I
Register Address Selection. These lines carry register addresses and
should be valid during any read or write operation.
Serial Control Data. Data for a read/write operation is clocked in or out
on the falling edge of the EXCLK pin. The direction of data flow is
controlled by the RD pin. RD low outputs data. RD high inputs data.
Read. A low on this input informs the 73K222AL that data or status
information is being read by the processor. The falling edge of the RD
signal will initiate a read from the addressed register. The RD signal
must continue for eight falling edges of EXCLK in order to read all eight
bits of the referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.
Write. A low on this input informs the 73K222AL that data or status
information has been shifted in through the DATA pin and is available
for writing to an internal register. The normal procedure for a write is to
shift in data LSB first on the DATA pin for eight consecutive falling
edges of EXCLK and then to pulse WR low. Data is written on the
rising edge of WR.
DESCRIPTION
Write. A low on this informs the 73K222AL that data is available on
AD0-AD7 for writing into an internal register. Data is latched on the
rising edge of WR. No data is written unless both WR and the latched
CS are low.
(continued)
5
V.22, V.21, Bell 212A, 103
Single-Chip Modem
73K222AL