spl505yc256bst SpectraLinear Inc, spl505yc256bst Datasheet - Page 27

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spl505yc256bst

Manufacturer Part Number
spl505yc256bst
Description
Clock Generator For Intel Bearlake Chipset
Manufacturer
SpectraLinear Inc
Datasheet
Rev 1.4 March 21, 2007
Document History Page
Document Title: SPL505YC256BT/
REV.
1.0
1.1
1.2
1.3
1.4
Issue Date
12/13/06
1/30/07
2/06/07
3/06/07
3/21/07
Change
Orig. of
JMA
JMA
JMA
JMA
JMA
New data sheet
1. Added SE1/SE2 to pinout in pinout diagram
2. Added clarifications to Byte 11
3. Added new definitions to Byte 13
4. Added PCI3/CFG0 voltage requirements in DC parameters
1. Changed Byte11 Bit 0 from 1 to 0; CPU2 to Stopped with CPU_STP#
2. Changed Byte 13 Bit 4 from 1 to 0; SATA spread default off
3. Changed Byte 13 Bit 2 from 0 to 1; SE drive strength default tohigh
4. Changed Byte 13 Bit 1 from 0 to 1; Reserved bit
6. Changed 1394A ppm from +/-100ppm to +/-30ppm
5. Added 1394B
6. Added CPU0 to CPU1 100ps skew spec
7. 25M typo on 1394A removed
8. FSD in overclocking description removed.
1. Part number changes due to part revision
2. Revision ID changed from 0000 to 0001 in Byte 7[7:4]
3. Added Byte 18 for additional single-ended drive strength control
1. Specified Triangular Spread Spectrum Profile
2. Removed IEEE clocks
3. RESERVED Byte 13 Bit5 - Engineering spread percentage -0.47%
SPL505YC256BS Clock Generator for Intel
Description of Change
SPL505YC256BT/
SPL505YC256BS
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®
Bearlake Chipset

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