ak4113 AKM Semiconductor, Inc., ak4113 Datasheet - Page 33

• Manufacturer Part Number: ak4113
• Description: 192khz 24bit Dir With 6 1 Selector
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
2. I
The AK4113 supports a fast-mode I
2-1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4113
recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the
SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the
SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the
master device.
2-1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
2-1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
MS0349-E-02
2
C bus control mode (I2C pin = “H”)
SCL
SDA
SCL
SDA
START CONDITION
2
C-bus system (max : 400kHz).
Figure 33. START and STOP conditions
DATA VALID
DATA LINE
STABLE :
Figure 32. Data transfer
- 33 -
CHANGE
OF DATA
ALLOWED
STOP CONDITION
[AK4113]
2005/08