ak4683 AKM Semiconductor, Inc., ak4683 Datasheet - Page 46

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ak4683

Manufacturer Part Number
ak4683
Description
Asynchronous Multi-channel Audio Codec With Dir/t
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4683
has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel
status, the AK4683 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz).
The PLL loses lock when the received sync interval is incorrect.
When DIR is selected. the CM0/CM1 bits select the clock source and the data source of SDTO. In Mode 2, the clock
source is automatically switched from PLL to XTI/MCLK2 when PLL goes unlock state. In Mode 3, the clock source is
fixed to XTI/MCLK2, but PLL is also operating and the recovered data such as C bits can be monitored. For Mode 2
and 3, it is recommended that the frequency of XTI/MCLK2 is different from the recovered frequency from PLL.
When 384fs of XTI/MCLK2 is supplied to DIR/DIT, CKSDT bit should be set to “1”.
MS0427-E-02
192kHz Clock Recovery
Clock Operation Mode
Mode
0
1
2
3
CM1
0
0
1
1
CKSDT bit
ON: Oscillation (Power-up), OFF: STOP (Power-down)
CM0
0
1
0
1
0
1
OPERATION OVERVIEW (DIR/DIT part)
Table 45. Clock Operation Mode select
UNLOCK
Table 46. XTI/MCLK2 speed
0
1
-
-
-
OFF
Clock Speed
PLL
ON
ON
ON
ON
- 46 -
x 2/3
x 1
Clock source
EXTCLK
EXTCLK
EXTCLK
PLL
PLL
SDTO
RX
DIT source
RX
DIT source
DIT source
(default)
(default)
[AK4683]
2007/04

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