ak4683 AKM Semiconductor, Inc., ak4683 Datasheet - Page 43

• Manufacturer Part Number: ak4683
• Description: Asynchronous Multi-channel Audio Codec With Dir/t
• Manufacturer: AKM Semiconductor, Inc.

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The status of analog output pins is as follows.
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When RSTN1 bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog
outputs go to VCOM voltage, DZF/OVF pin goes to “H” and SDTOA/B pins go to “L”. Because some click noise
occurs, the analog output should be muted externally if the click noise influences system application. The Figure 24
shows the power-up sequence.
Notes:
MS0427-E-02
Status of analog output pins during power-down (PDN pin =”L”)
Reset Function
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
(5) When RSTN1 bit = “0”, the analog outputs go to VCOM voltage.
(6) Click noise occurs at 4∼5/fs after RSTN1 bit becomes “0”, and occurs at 1∼2/fs after RSTN1 bit becomes “1”.
(7) The external clocks (MCLK, BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode. When
(8) DZF pins go to “H” when the RSTN1 bit becomes “0”, and go to “L” at 6~7/fs after RSTN1 bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN1 bit “0” to the internal RSTN bit “0”.
delay (GD).
noise influences system application.
This noise is output even if “0” data is input.
exiting the reset mode, “1” should be written to RSTN1 bit after the external clocks (MCLK, BICKA (BICKB),
LRCKA (LRCKB)) are fed.
Pin Name
HPL/HPR
LOUT1/ROUT1/LOUT2/ROUT2
LISEL/RISEL
DAC Internal
DAC In
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
DAC Out
ADC Internal
ADC In
ADC Out
RSTN bit
Internal
RSTN bit
(Digital)
(Analog)
(Analog)
(Digital)
State
State
Normal Operation
Normal Operation
GD
Figure 24. Reset sequence example
GD
(2)
(2)
Digital Block Power-down
Digital Block Power-down
(6)
(7)
4~5/fs (9)
Don’t care
“0”data
“0”data
(5)
- 43 -
(3)
(6)
1~2/fs (9)
HVSS
VCOM
Hi-Z
4∼5/fs (8)
Init Cycle
516/fs
(1)
Normal Operation
(4)
Normal Operation
GD
GD
[AK4683]
2007/04