ak4645 ETC-unknow, ak4645 Datasheet - Page 91

• Manufacturer Part Number: ak4645
• Description: Stereo Codec With Mic/hp-amp
• Manufacturer: ETC-unknow

ASAHI KASEI
MS0543-E-00
Headphone-amp Output
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4645 is PLL mode, DAC and Headphone-Amp should
(2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1”
(3) Set up the low frequency boost level (BST1-0 bits)
(4) Set up the input digital volume (Addr: 09H and 0CH)
(5) Set up the output digital volume (Addr: 0AH and 0DH)
(6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1”
(7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1”
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
(9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0”
(10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0”
(11) Power down DAC and MIN-Amp: PMDAC = PMMIN bits = “1” → “0”
(12) Off the bass boost: BST1-0 bits = “00”
(13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0”
(Addr:05H, D5&D2-0)
(Addr:0AH&0DH, D7-0)
(Addr:09H&0CH, D7-0)
DVL/R7-0 bits
PMHPL/R bits
(Addr:01H, D5-4)
(Addr:0EH, D3-2)
IVL/R7-0 bits
(Addr:0FH, D0)
BST1-0 bits
(Addr:00H, D2)
(Addr:00H, D5)
(Addr:01H, D6)
HPL/R pins
HPMTN bit
PMDAC bit
PMMIN bit
DACH bit
FS3-0 bits
be powered-up in consideration of PLL lock time after a sampling frequency is changed.
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or
PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
Output voltage of headphone-amp is still HVSS.
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to
GND, the pop noise occurs. It takes twice of
The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is
0,000
E1H
18H
00
(1)
(3)
(2)
Figure 81. Headphone-Amp Output Sequence
(4)
(5)
(6)
(7)
(8)
Normal Output
10
1,111
91H
28H
τ
- 91 -
f
that the common voltage goes to GND.
(9)
(10)
τ
τ
(11)
r
f
= 100ms(typ), 250ms(max).
= 100ms(typ), 250ms(max).
(12)
00
(13)
E x a m p le :
P L L M a s te r M o d e
S a m p lin g F r e q u e n c y : 4 4 . 1 k H z
D V O L C b it = “ 1 ” ( d e fa u lt )
D ig ita l V o lu m e L e v e l: − 8 d B
B a s s B o o s t L e v e l: M id d le
D e - e m p h a s e s r e s p o n s e : O F F
S o ft M u te T im e : 2 5 6 /fs
( 1 ) A d d r : 0 5 H , D a t a :2 7 H
( 2 ) A d d r : 0 F H , D a ta 0 9 H
( 3 ) A d d r : 0 E H , D a t a 1 9 H
( 4 ) A d d r : 0 9 H & 0 C H , D a t a 9 1 H
( 5 ) A d d r : 0 A H & 0 D H , D a ta 2 8 H
( 6 ) A d d r : 0 0 H , D a t a 6 4 H
( 7 ) A d d r : 0 1 H , D a t a 3 9 H
( 8 ) A d d r : 0 1 H , D a t a 7 9 H
( 9 ) A d d r : 0 1 H , D a t a 3 9 H
( 1 0 ) A d d r :0 1 H , D a t a 0 9 H
( 1 1 ) A d d r :0 0 H , D a t a 4 0 H
( 1 2 ) A d d r :0 E H , D a ta 0 0 H
( 1 3 ) A d d r :0 F H , D a ta 0 8 H
P la y b a c k
[AK4645]
2006/09