ak4645 ETC-unknow, ak4645 Datasheet - Page 28
ak4645
Manufacturer Part Number
ak4645
Description
Stereo Codec With Mic/hp-amp
Manufacturer
ETC-unknow
Datasheet
1.AK4645.pdf
(96 pages)
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ASAHI KASEI
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4645 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 5).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 10) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (see Table 6).
MS0543-E-00
PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
AK4645
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
256fs/128fs/64fs/32fs
≥ 32fs
1fs
- 28 -
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
MCLK
BCLK
LRCK
SDTI
SDTO
DSP or µP
[AK4645]
2006/09