ak4642e AKM Semiconductor, Inc., ak4642e Datasheet - Page 27

• Manufacturer Part Number: ak4642e
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4642 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (see Table 5).
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6).
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4642 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external
clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”).
MS0420-E-00
PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
Figure 15. PLL Slave Mode 2 (PLL Reference Clock: LRCK or BICK pin)
Figure 14. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
AK4642
AK4642
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
256fs/128fs/64fs/32fs
≥ 32fs
1fs
32fs, 64fs
- 27 -
1fs
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
MCLK
BCLK
LRCK
SDTI
SDTO
BCLK
LRCK
SDTI
SDTO
DSP or µP
DSP or µP
[AK4642EN]
2005/09