ak4647vq AKM Semiconductor, Inc., ak4647vq Datasheet - Page 21

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ak4647vq

Manufacturer Part Number
ak4647vq
Description
Stereo Codec With Mic/hp-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet
ASAHI KASEI
„ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the
MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by
PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. The BICK output frequency is selected among 32fs or
64fs, by BCKO bit (see Table 10).
MS0566-E-00
Mode
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
0
1
2
3
AK4647
Table 10. BICK Output Frequency at Master Mode
BCKO bit
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
PS1 bit
0
1
0
0
1
1
Figure 13. PLL Master Mode
256fs/128fs/64fs/32fs
32fs, 64fs
PS0 bit
BICK Output
1fs
Frequency
- 21 -
0
1
0
1
32fs
64fs
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
MCKO pin
MCLK
BCLK
LRCK
SDTI
SDTO
256fs
128fs
64fs
32fs
Default
DSP or P
Default
[AK4647]
2006/11

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