ak4647 AKM Semiconductor, Inc., ak4647 Datasheet
ak4647
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ak4647 Summary of contents
Page 1
... ASAHI KASEI The AK4647 features a stereo CODEC with a built-in Microphone-Amplifier and Headphone-Amplifier. Built-in PLL circuit supports an easy interface with variable systems. The AK4647 is available in a 48pin LQFP, utilizing less board space than competitive offerings. 1. Recording Function • Stereo Mic Input (Full-differential or Single-ended) • ...
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... Wind-Noise MIC-Amp A/D HPF Reduction Separation PMADR PMLO PMHPL PMDAC DATT Bass D/A ALC SMUTE Boost PMHPR PMBP MIN HVSS Figure 1. Block Diagram - 2 - [AK4647 DVDD DVSS I2C CSN Control Register CCLK CDTI PDN Stereo ALC BICK LRCK SDTO SDTI Audio I/F Stereo HPF ...
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... ASAHI KASEI Ordering Guide −40 ∼ +85°C AK4647VN AKD4647 Evaluation board for AK4647 Pin Layout ROUT 39 LOUT MIN RIN2/IN2− LIN2/IN2+ 45 LIN1/IN1− RIN1/IN1+ MPWR 48 MS0566-E-00 48pin LQFP (0.5mm pitch AK4647VQ 19 18 Top View ...
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... Audio Serial Data Clock Pin 22 DVDD - Digital Power Supply Pin 23 DVSS - Digital Ground Pin No Connect internal bonding. This pin should be left floating. MS0566-E-00 PIN/FUNCTION Function 2 C Bus, “L”: 3-wire Serial 2 C Bus Mode Bus Mode Bus Mode [AK4647] 2006/11 ...
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... Microphone Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input) 48 MPWR O MIC Power Supply Pin Note 1. All input pins except analog input pins (MIN, LIN1, RIN1, LIN2, RIN2) should not be left floating. Note 2. AVDD or AVSS voltage should be input to I2C pin. MS0566-E-00 Function - 5 - [AK4647] 2006/11 ...
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... Note 7. The power-up sequence between AVDD, DVDD and HVDD is not critical. When the power supplies are partially powered OFF, the AK4647 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. When AVDD or HVDD is powered OFF, the power supply current of DVDD at power-down mode may be increased ...
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... Units 60 80 kΩ kΩ + + + 0.228 Vpp - 0.114 Vpp - 0.057 Vpp 2. kΩ ...
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... HPL/HPR pin 47μF 6.8Ω Figure 2. Headphone-Amp output circuit - 8 - [AK4647] typ max Units - 16 Bits 1.98 2.18 Vpp 2.50 2.75 Vpp 88 - dBFS 100 - dB 0.1 0 kΩ 1.98 2.38 Vpp 3.00 3.60 ...
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... Note 20. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMBP bits = “1” and PMSPK bit = “0”. Note 21. All digital input pins are fixed to DVDD or DVSS. MS0566-E-00 min typ - 1.98 −4 −24.5 −20 −16 [AK4647] max Units - Vpp +4 −15 μA 100 2006/11 ...
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... Note 25. These frequency responses scale with fs high-level and low frequency signal is input, the analog output clips to the full-scale. MS0566-E-00 FILTER CHARACTERISTICS Symbol min 26 Δ 25 [AK4647] typ max Units - 17.3 kHz 19.4 - kHz 19.9 - kHz 22.1 - kHz - - kHz ±0 1/fs μ 19.6 kHz 20.0 - kHz 22.05 - kHz - - kHz ±0. ...
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... Duty - tBCK - tBCK - dBCK - fCLK 11.2896 tCLKL 0.4/fCLK tCLKH 0.4/fCLK fMCK 0.2352 dMCK 40 dMCK - fs 7.35 Duty 45 tBCK 1/(64fs) tBCKL 0.4 x tBCK tBCKH 0.4 x tBCK - 11 - [AK4647] typ Max Units - - V - 30%DVDD 0 0.4 V ±10 μA - typ max Units - 27 MHz - - 12.288 MHz 50 60 ...
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... Units 48 kHz 55 % 1/(32fs kHz 12.288 MHz 13.312 MHz 13.312 MHz - kHz 26 kHz 13 kHz 55 ...
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... registered trademark of Philips Semiconductors. Note 28. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 29. The AK4647 can be reset by the PDN pin = “L”. Note 30. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. ...
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... Figure 4. Audio Interface Timing (PLL Master mode) MS0566-E-00 1/fCLK tCLKL 1/fs tLRCKH tLRCKL Duty = tLRCKH 100 tLRCKL 100 1/fMCK tMCKL dMCK = tMCKL x fMCK x 100 tBCKL tLRD tSDS tSDH - 14 - [AK4647] VIH VIL 50%DVDD 50%DVDD 50%DVDD 50%DVDD tBSD 50%DVDD VIH VIL 2006/11 ...
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... Duty = tLRCKH 100 tLRCKH tLRCKL tBCK tBCKH tBCKL Figure 6. Clock Timing (EXT Slave mode [AK4647] VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL tLRCKL 100 VIH VIL ...
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... MS0566-E-00 tLRB tBSD MSB tSDS tSDH tCSS tCCKL tCCKH tCDS C1 C0 Figure 8. WRITE Command Input Timing tCSH D1 D0 Figure 9. WRITE Data Input Timing - 16 - [AK4647] VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL VIH VIL tCCK tCDH VIH R/W VIL tCSW VIH ...
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... PMADR bit SDTO Timing PDN MS0566-E-00 tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 10 Bus Mode tPDV Figure 11. Power Down & Reset Timing 1 tPD Figure 12. Power Down & Reset Timing [AK4647] VIH VIL tSP VIH VIL tSU:STO Stop 50%DVDD VIL 2006/11 ...
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... AK4647 goes to master mode by changing M/S bit = “1”. When the AK4647 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4647 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state ...
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... When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4647 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. ...
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... Output See Table 9 MCKO pin MCKO bit = “0” “1” “L” Output “L” Output “L” Output - 20 - [AK4647] BICK pin LRCK pin “L” Output “L” Output Invalid Invalid See Table 10 1fs Output “1”. ...
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... DSP or μP 256fs/128fs/64fs/32fs MCLK 32fs, 64fs BCLK 1fs LRCK SDTI SDTO Figure 13. PLL Master Mode PS1 bit PS0 bit MCKO pin 0 0 256fs 0 1 128fs 1 0 64fs 1 1 32fs BICK Output Frequency 0 32fs Default 1 64fs - 21 - [AK4647] Default 2006/11 ...
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... PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4647 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4). a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output ...
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... The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4647 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “ ...
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... The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4647 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “ ...
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... MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4647 in master mode, but must be input to the AK4647 in slave mode. The SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). ...
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... Lch Data Figure 20. Mode 3 Timing ADC Lch data 0 All “0” 1 Rch Input Signal 0 Lch Input Signal 1 Lch Input Signal Table 14. Mono/Stereo ADC operation - 26 - [AK4647 ...
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... MIC/LINE Input Selector The AK4647 has input selector. When MDIF1 and MDIF2 bits are “0”, INL and INR bits select LIN1/LIN2 and RIN1/RIN2, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− ...
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... INR bit MDIF2 bit Figure 21. Mic/Line Input Selector MPWR pin MIC-Amp IN1− pin IN1+ pin A/D INL0 bit INR1 bit INR0 bit [AK4647] ADC Lch ADC Rch AK4647 SDTO pin Lch Rch 1 RIN2 IN1+/− 1 LIN2 RIN2 2006/11 ...
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... ASAHI KASEI MIC Gain Amplifier The AK4647 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 18). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. ...
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... ASAHI KASEI Digital EQ/HPF/LPF The AK4647 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data (Figure 24). FIL1, FIL3 and EQ blocks are IIR filters of 1 order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” ...
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... Amplitude 2 − 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) 1 − tan (πfc/fs tan (πfc/fs) Amplitude 2 + 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs [AK4647] Phase (B+1)sin (2πf/fs) − (B−1)cos (2πf/fs) Phase (B−1)sin (2πf/fs) − (B+1)cos (2πf/fs) 2006/11 ...
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... /fs tan (πfc /fs Amplitude 2ACcos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) =3000Hz, Gain=+8dB 2 fc Frequency [AK4647] 1 − tan (πfc /fs) 2 K/ tan (πfc /fs) 1 Phase (AB−C)sin (2πf/fs) − (AB+C)cos (2πf/fs) 13 2006/11 ...
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... Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms - 33 - [AK4647] ALC Power-down Default Playback path Recording path Recording path Recording path Default 0.375dB Default 0.750dB 1.500dB 3.000dB 0.375dB 44.1kHz 2.9ms Default 5 ...
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... RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 27. ALC Recovery GAIN Step GAIN(dB) Step +36.0 +35.625 +35.25 : +30.375 +30.0 0.375dB +29.625 : −53.25 −53.625 −54.0 MUTE - 34 - [AK4647] 44.1kHz 2.9ms Default 5.8ms 11.6ms 23.2ms Default Default 2006/11 ...
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... Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” (1) Addr=06H, Data=14H (3) Addr=09H&0CH, Data=E1H the same or smaller than REF’ [AK4647] fs=44.1kHz Data Operation −4.1dBFS 01 0 Enable 11 23.2ms 11 23 ...
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... Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H MS0566-E-00 GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 +30.0 0.375dB +29.625 : −53.25 −53.625 −54 MUTE Table 30. Input Digital Volume Setting - 36 - [AK4647] Default 2006/11 ...
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... When ALC is enabled again, ALC bit should be set to “1” interval more than zero crossing timeout period after ALC bit = “0”. MS0566-E-00 Enable E1H(+30dB) C6H(+20dB) E1(+30dB) --> F1(+36dB) E1(+30dB) (1) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB [AK4647] Disable 2006/11 ...
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... ASAHI KASEI De-emphasis Filter The AK4647 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 31). DEM1 Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 32). If the BST1-0 bits are set to “ ...
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... ASAHI KASEI Digital Output Volume The AK4647 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “ ...
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... Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0566-E- bit ( (2) Figure 28. Soft Mute Function - 40 - [AK4647] ( 2006/11 ...
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... Table 36. MIN Input MS0566-E-00 BEEPL BEEPH Figure 29. Block Diagram of MIN pin MIN LOUT/ROUT 0dB +2dB LOUT/ROUT Output Gain (typ MIN HPL/HPR −20dB −16.4dB Headphone-Amp Output Gain (typ [AK4647 LOUT/ROUT pin HPL/HPR pin Default = 20kΩ i Default = 20kΩ i 2006/11 ...
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... LOUT/ROUT pin Power-down Pull-down to AVSS Normal Operation Normal Operation Power-save Fall down to AVSS Power-save Rise up to VCOM Gain Output Voltage (typ) 0dB 0.6 x AVDD Default +2dB 0.757 x AVDD LOUT 1μF 220Ω ROUT - 42 - [AK4647] LOUT pin ROUT pin Default 20kΩ 2006/11 ...
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... LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0566-E- [AK4647 ≥ 2006/11 ...
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... Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are HVSS. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some POP noise occurs. MS0566-E-00 2.6 ∼ 5.25V 4.0 ∼ 5.25V 0 1 0.6 x AVDD 0.91 x AVDD 22Ω 100Ω “0”: 500ms(max) (3) ( [AK4647] 2006/11 ...
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... MS0566-E- Headphone 16Ω 0.22μ 10Ω fc [Hz] fc [Hz] BOOST=OFF BOOST=MIN @fs=44.1kHz 70 28 149 106 100 137 69 Table 40. External Circuit Example - 45 - [AK4647] is 16Ω. Output powers are shown at L Output Power [mW]@0dBFS 2.7V 3.0V 3.3V 10.1 12.5 15.1 5.1 6.3 7 0.9 1.1 1.3 2006/11 ...
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... R/W “1” Chip Address (C1 = “1” “0”); Fixed to “10” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 35. Serial Control I/F Timing - 46 - [AK4647] 2006/11 ...
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... HIGH defines a STOP condition (Figure 42). The AK4647 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4647 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred ...
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... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4647. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...
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... MASTER S START CONDITION SDA SCL MS0566-E-00 Figure 42. START and STOP Conditions Figure 43. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 44. Bit Transfer on the I C-Bus - 49 - [AK4647] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2006/11 ...
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... EQA12 EQB6 EQB5 EQB4 0 0 EQB13 EQB12 EQC6 EQC5 EQC4 EQC14 EQC13 EQC12 F1A6 F1A5 F1A4 0 F1A13 F1A12 F1B6 F1B5 F1B4 0 0 F1B13 F1B12 - 50 - [AK4647 PMLO PMDAC 0 PMADL M/S 0 MCKO PMPLL 0 PMMP 0 MGAIN0 0 BEEPL 0 0 BCKO 0 DIF1 DIF0 0 FS2 FS1 ...
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... PDN pin should be “L”. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0566-E- PMVCM PMBP 0 PMLO [AK4647 PMDAC 0 PMADL 2006/11 ...
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... When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. MS0566-E- HPMTN PMHPL PMHPR DACL [AK4647 M/S 0 MCKO PMPLL PMMP 0 MGAIN0 ...
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... LOPS 0 MGAIN1 PLL3 PLL2 PLL1 PLL0 PS1 PS0 FS3 [AK4647 BEEPL BCKO 0 DIF1 DIF0 FS2 FS1 FS0 ...
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... D4 0 ZTM1 ZTM0 ALC ZELMN REF6 REF5 REF4 [AK4647 WTM1 WTM0 LMAT1 LMAT0 LMTH0 RGAIN0 REF3 REF2 REF1 REF0 ...
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... DVR6 DVR5 DVR4 LMTH1 LOOP SMUTE DVOLC [AK4647 IVL3 IVL2 IVL1 IVL0 IVR3 IVR2 IVR1 IVR0 DVL3 DVL2 DVL1 DVL0 DVR3 DVR2 DVR1 DVR0 1 0 ...
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... HPG: Headphone-Amp Gain Select (see Table 39) 0: 0dB (Default) 1: +3.6dB MS0566-E- HPG MDIF2 [AK4647 IVOLC HPM BEEPH DACH MDIF1 INR INL PMADR 2006/11 ...
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... Disable (Default) 1: Enable When FIL1 bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block is through (0dB). MS0566-E- GN1 GN0 0 FIL1 [AK4647 FIL3 2006/11 ...
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... EQC14 EQC13 EQC12 F1A7 F1A6 F1A5 F1A4 F1AS 0 F1A13 F1A12 F1B7 F1B6 F1B5 F1B4 0 0 F1B13 F1B12 [AK4647 F3A3 F3A2 F3A1 F3A0 F3A11 F3A10 F3A9 F3A8 F3B3 F3B2 F3B1 F3B0 F3B11 F3B10 F3B9 F3B8 EQA3 EQA2 EQA1 ...
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... When the AK4647 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4647 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. - When the AK4647 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. ...
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... When the AK4647 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4647 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. - When the AK4647 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. ...
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... If AVDD, DVDD and HVDD are supplied separately, the power-up sequence is not critical. AVSS, DVSS and HVSS of the AK4647 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board ...
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... MCKO pin <Example> (1) After Power Up, PDN pin = “L” “L” time of 150ns or more is needed to reset the AK4647. (2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period. (3) Power UpVCOM: PMVCM bit = “0” VCOM should first be powered-up before the other block operates. ...
Page 63
... Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4647. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...
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... LRCK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4647. (2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...
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... BICK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4647. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...
Page 66
... Registers set-up sequence at ALC operation” At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4647 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H) ...
Page 67
... At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4647 is PLL mode, DAC and Headphone-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” ...
Page 68
... ROUT pin <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). When the AK4647 is PLL mode, DAC and Stereo Line-Amp should be powered-up in consideration of PLL lock time after the sampling frequency is changed. (2) Set up the path of “DAC (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “ ...
Page 69
... Input Master Clock Select at PLL Mode: 11.2896MHz (1) (2) Addr:01H, Data:08H (3) Stop an external MCKI Figure 54. Clock Stopping Sequence (1) Example Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Figure 55. Clock Stopping Sequence ( [AK4647] (1) Addr:01H, Data:00H (2) Stop the external clocks 2006/11 ...
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... Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs Figure 56. Clock Stopping Sequence (3) Example Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Figure 57. Clock Stopping Sequence ( [AK4647] (1) Addr:01H, Data:00H (2) Stop the external clocks (1) Stop the external clocks 2006/11 ...
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... ASAHI KASEI 48pin LQFP(Unit:mm) 9.0 ± 0.2 7 0.22 ± 0.08 0.5 0.10 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0566-E-00 PACKAGE 1.70Max 25 1.40 ± ° ∼ 10° 0.5 ± 0.2 Epoxy Cu Solder (Pb free) plate - 71 - [AK4647] 0.13 ± 0.13 0.16 ± 0.07 2006/11 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0566-E-00 MARKING AK4647VQ XXXXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Page Contents MPORTANT NOTICE - 72 - [AK4647] 2006/11 ...