ak4555 AKM Semiconductor, Inc., ak4555 Datasheet - Page 7

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ak4555

Manufacturer Part Number
ak4555
Description
Low Power & Small Package 20bit ?? Codec
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
(Ta=25°C; VDD=1.6 ∼ 3.6V; C
Master Clock Timing
LRCK Timing
Serial Interface Timing
Reset Timing
Note 8. SCLK rising edge must not occur at the same time as LRCK edge.
Note 9. These cycles are the number of LRCK rising from PWADN rising.
MS0363-E-01
Frequency
Duty Cycle
Frequency
Duty Cycle
SCLK Period
SCLK Pulse Width Low
LRCK Edge to SCLK “↑”
SCLK “↑” to LRCK Edge
SCLK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
PWADN or PWDAN Pulse Width
PWADN “↑” to SDTO Valid
Pulse Width High
Parameter
256fs/384fs/512fs/768fs
1024fs
(8kHz ≤ fs ≤ 33kHz)
(33kHz < fs ≤ 50kHz)
L
=20pF)
(Note 8)
(Note 8)
(Note 9)
SWITCHING CHARACTERISTICS
Symbol
tSCKH
tSCKL
dCLK
tPWV
fCLK
fCLK
tSCK
tSCK
tSDH
tLRS
tSLR
tDSS
tSDS
Duty
tPW
fs
- 7 -
1/(96fs)
2.048
312.5
2.048
min
130
130
150
40
45
50
50
50
50
8
-
-
2081
44.1
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
38.4
25.6
50
55
80
60
-
-
-
-
-
-
-
-
-
-
[AK4555]
Units
MHz
MHz
2005/08
kHz
1/fs
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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