ak4560a AKM Semiconductor, Inc., ak4560a Datasheet - Page 16

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ak4560a

Manufacturer Part Number
ak4560a
Description
16bit Codec With Alc And Mic/hp/spk-amps
Manufacturer
AKM Semiconductor, Inc.
Datasheet
ASAHI KASEI
n Audio Interface Format
Data is shifted in/out the SDTI/SDTO pins using BCLK and LRCK inputs. The serial data is MSB-first, 2's compliment
format, ADC is MSB justified and DAC is LSB justified.
n Control Register Timing
The data on the 3-wire serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first,
8bit). The Transmitting data is output to each bit by “ ” of CCLK, the receiving data is latched by “ ” of CCLK. Writing
data becomes effective by “ ” of CS . Reading data becomes Hi-z (floating) by “ ” of CS . CS should be held to “H”
at no access.
CCLK always need 16 edges of “ ” during CS . Reading/Writing of the address except 00H 09H are inhibited.
Reading/Writing of the control registers by except op1-0 = “11” are invalid.
In case of reading data, nothing is written to D0 D7 data.
MS0028-E-00
BCLK(32fs)
SDTO(o)
SDTI(i)
BCLK(64fs)
SDTO(o)
SDTI(i)
LRCK
CS
CCLK
CDTIO
0
0
15
15
15:MSB, 0:LSB
1
1
14
14
op0
"1"
2
2
Don’t Care
0
13
13
3
3
op0 -op2: Op -code (111:WRITE, 110:READ)
A0 -A4:
D0 -D7:
op1
"1" "X"
1
8
13
8
op2
7
2
2
9
14
Lch Data
A0
6
1
3
Address
Control Data
10
15
5
0
A1
11
16
4
Figure 9. Control Data Timing
Figure 8. Audio Data Timing
15 14
4
A2
12
17
5
3
13
18
A3
6
2
14
A4
- 16 -
1
7
1
15
31
D0
0
0
8
0
0
15 14
15 14
D1
9
1
1
D2
10
2
2
13
13
Don’t Care
D3
3
3
11
8
1
8
12
D4
7
2
Rch Data
9
14
13
D5
6
1
10
15
14
D6
5
0
11
16
15 14
D7
4
15
12
17
3
13
18
2
14
1
1
15
31
[AK4560A]
0
0
2000/05
0
0
15
15
1
1

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