ak4527b AKM Semiconductor, Inc., ak4527b Datasheet - Page 22

• Manufacturer Part Number: ak4527b
• Description: High Performance Multi-channel Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n Serial Control Interface
The AK4527B can control its functions via registers. Internal registers may be written by 2 types of control mode. The
chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized. When the state of P/S pin is changed, the AK4527B should be reset by PDN pin.
MS0056-E-00
(1) 3-wire Serial Control Mode (I2C = “L”)
(2) I
consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”; Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock
speed of CCLK is 5MHz(max). The CSN pins should be held to “H” except for access.
address (2bits, CAD0/1), Read/Write (1bit, Fixed to “0”; Write only), Register address (MSB first, 5bits) and
Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of SCL and data is clocked out on
the falling edge. Data can be written after a high-to-low transition of SDA when SCL is “H”(start condition), and is
latched after a low-to-high transition of SDA when SCL is “H”(stop condition). The clock speed of SCL is
100kHz(max). The CSN pin should be connected to DVDD at I
register address auto increment capability.
* Writing to control register is invalid when PDN = “L” or the MCLK is not fed.
* AK4527B does not support the read command.
Internal registers may be written to the 3 wire µP interface pins (CSN,CCLK and CDTI). The data on this interface
Internal registers may be written to I
2
C Bus Control Mode (I2C = “H”)
SDA
SCL
CCLK
CSN
CDTI
Start
0
0
1
C1
0
0
C0
1
0
R/W
C1 C0
Figure 8. 3-wire Serial Control I/F Timing
2
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W:
A4-A0: Register Address
D7-D0: Control Data
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W:
A4-A0: Register Address
D7-D0: Control Data
ACK: Acknowledge
R/W
Figure 9. I
2
A4
C Bus interface pins: SCL & SDA. The data on this interface consists of Chip
3
ACK
A3
4
Read/Write (Fixed to “1” : Write only)
Read/Write (Fixed to “0” : Write only)
0
A2
5
2
C-bus Control I/F Timing
0
A1
6
0 A4 A3 A2 A1 A0
- 22 -
A0
7
D7
8
D6
2
9
C Bus control mode. The AK4527B does not have a
D5
10
ACK
D4
11
D7 D6 D5 D4 D3 D2 D1 D0
D3
12
D2
13
D1
14
D0
15
ACK
Stop
[AK4527B]
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