adf7023-j Analog Devices, Inc., adf7023-j Datasheet - Page 38

• Manufacturer Part Number: adf7023-j
• Description: High Performance, Low Power, Ism Band Fsk/gfsk/msk/gmsk Transceiver Ic
• Manufacturer: Analog Devices, Inc.

ADF7023-J
PACKET MODE
The on-chip communications processor can be configured for
use with a wide variety of packet-based radio protocols using
2FSK/GFSK/MSK/GMSK modulation. The general packet
format, when using the packet management features of the
communications processor, is illustrated in Table 16. To use the
packet management features, the DATA_MODE setting in the
PACKET_LENGTH_CONTROL register (Address 0x126)
should be set to packet mode; 240 bytes of dedicated packet
RAM are available to store, transmit, and receive packets. In
transmit mode, preamble, sync word, and CRC can be added by
the communications processor to the data stored in the packet
RAM for transmission. In addition, all packet data after the
sync word can be optionally whitened, Manchester encoded, or
8b/10b encoded on transmission and decoded on reception.
In receive mode, the communications processor can be used to
qualify received packets based on the preamble detection, sync
word detection, CRC detection, or address match and generate
an interrupt on the IRQ_GP3 pin. On reception of a valid packet,
the received payload data is loaded to packet RAM memory.
More information on interrupts is contained in the Interrupt
Generation section.
PREAMBLE
The preamble is a mandatory part of the packet that is automatically
added by the communications processor when transmitting a
packet and removed after receiving a packet. The preamble is a
0x55 sequence, with a programmable length between 1 byte
and 256 bytes, that is set in the PREAMBLE_LEN register
Table 16. ADF7023-J Packet Structure Description
Packet Format Options
Field Length
Optional Field in Packet Structure
Comms Processor Adds in Tx, Removes in Rx
Host Writes These Fields to Packet RAM
Whitening/Dewhitening (Optional)
Manchester Encoding/Decoding (Optional)
8b/10b Encoding/Decoding (Optional)
Configurable Parameter
Receive Interrupt on Valid Field Detection
Programmable Field Error Tolerance
Programmable Field Offset (See Figure 55)
1
Yes indicates that the packet format option is supported, and X indicates that the packet format option is not supported.
Preamble
1 byte to
256 bytes
X
Yes
X
X
X
X
Yes
Yes
Yes
X
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Sync
1 bit to 24 bits
X
Yes
X
X
X
X
Yes
Yes
X
Yes
(Address 0x11D). It is necessary to have preamble at the
beginning of the packet to allow time for the receiver AGC,
AFC, and clock and data recovery circuitry to settle before the
start of the sync word. The required preamble length depends
on the radio configuration. See the Radio Blocks section for
more details.
In receive mode, the ADF7023-J can use a preamble qualification
circuit to detect preamble and interrupt the host processor. The
preamble qualification circuit tracks the received frame as a
sliding window. The window is three bytes in length, and the
preamble pattern is fixed at 0x55. The preamble bits are examined
in 01pairs. If either bit or both bits are in error, the pair is deemed
erroneous. The possible erroneous pairs are 00, 11, and 10. The
number of erroneous pairs tolerated in the preamble can be set
using the PREAMBLE_MATCH register value (Address 0x11B)
according to Table 15.
Table 15. Preamble Detection Tolerance (PREAMBLE_MATCH,
Address 0x11B)
Value
0x0C
0x0B
0x0A
0x09
0x08
0x00
Length
Yes
Yes
Yes
1 byte
Yes
X
Yes
Yes
X
X
X
Packet Structure
Address
1 byte to
9 bytes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
X
Yes
X
Description
No errors allowed.
One erroneous bit-pair allowed in 12 bit-pairs.
Two erroneous bit-pairs allowed in 12 bit-pairs.
Three erroneous bit-pairs allowed in 12 bit-pairs.
Four erroneous bit-pairs allowed in 12 bit-pairs.
Preamble detection disabled.
Payload
Payload Data
0 bytes to
240 bytes
Yes
X
Yes
Yes
Yes
Yes
Yes
X
X
X
1
CRC
2 bytes
Yes
Yes
X
Yes
Yes
Yes
Yes
Yes
X
X
Postamble
2 bytes
X
Yes
X
X
X
X
X
X
X
X