ipm6210a Intersil Corporation, ipm6210a Datasheet - Page 11

• Manufacturer Part Number: ipm6210a
• Description: Precision Dual Pwm Controller And Linear Regulator For Notebook Cpus
• Manufacturer: Intersil Corporation

small addition of the clock frequency pulses. Synchronization of
the upper MOSFET turn-on pulses with the main clock enables
seamless transition between the operation modes.
Operation During Processor Mode Changes
The PWM1 controller is specially designed to provide “on the
fly” automatic core voltage changes required by some
advanced processors for mobile applications. Dual core
voltage and operation frequency scaling allows for significant
power savings without sacrificing system performance in
battery operation mode.
As processor mode changes can happen when chip is in
PWM or hysteretic mode, measures were taken to provide
equally fast response to these changes. As soon as a DAC
code change is received, the chip is forced into PWM mode
till transition completes regardless of the load level.
Operating the controller in the synchronous PWM mode
allows faster output voltage transitions especially when a
downward output voltage change is commanded.
I/O Converter Architecture
The I/O converter architecture is close to that of the core
converter. It has the same mode control logic and can operate
in a constant frequency PWM mode or in hysteretic mode
depending on the load level, but its structure is much simpler
mainly because of absence of the differential input amplifier and
the DAC. This controller is synchronized to the same clock as
the core converter, but 180 degrees out-of-phase. Thus, some
reduction of the input current ripple is achieved.
Some performance curves of I/O converter are shown on
Figure 9 and Figure 10.
Gate Control Logic
The gate control logic translates generated PWM signals into
the MOSFETs gate drive signals providing necessary
amplification, level shift and shoot-trough protection. Also, it
helps to optimize the IC performance over a wide range of the
operational conditions. As MOSFET switching time can very
dramatically from type to type and with input voltage variation,
the gate control logic provides adaptive dead time by
monitoring gate voltages of both upper and lower MOSFETs.
Protections
All three outputs are monitored and protected against extreme
overload, short circuit and undervoltage conditions. Both PWM
outputs are monitored and protected from overvoltage
conditions. A sustained overload on any output latches-off all
the converters and sets the PGOOD pin low. The chip
operation can be restored by cycling VCC voltage or EN pin.
Overcurrent Protection
Both PWM controllers use the lower MOSFET’s
on-resistance - r
against shorted outputs. The sensed voltage drop after
amplification is compared with an internally set threshold.
DS(ON)
to monitor the current for protection
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IPM6210A
Several scenarios of the current protection circuit behavior
are possible.
If load step is strong enough to pull output voltage lower
than the undervoltage threshold, chip shuts down. If the
output voltage sag does not reach the undervoltage
threshold but the current exceeds the overcurrent
threshold, the pulse skipping circuit is activated. This
breaks the output voltage regulation and limits the current
supplied to the load.
Because of the nature of the current sensing technique,
and to accommodate a wide range of the r
the value of the threshold should represent overload
current about 180% of the nominal value. To decrease
current protection circuit noise susceptibility, a time delay
circuit (8:1 counter which counts the clock cycles) is
activated when the overcurrent condition is detected for the
first time. If after the delay the overcurrent condition
persists, the converter shuts down. If not - normal operation
is restored.
FIGURE 9. I/O CONVERTER LOAD TRANSIENT IN PWM MODE
1
1
2
2
FIGURE 10. I/O CONVERTER LOAD TRANSIENT WITH MODE
Ch1 50mV
Ch1 50mV
V
V
IO
IO
I
IO
CHANGE
I
IO
Ch2 500mA
Ch2 500mA
M50ms
M50µs
DS(ON)
variation,