ipm6210a Intersil Corporation, ipm6210a Datasheet - Page 10

• Manufacturer Part Number: ipm6210a
• Description: Precision Dual Pwm Controller And Linear Regulator For Notebook Cpus
• Manufacturer: Intersil Corporation

The zero frequency, the amplifier high-frequency gain and
the modulator gain are chosen to satisfy most of typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within 10kHz...50kHz range gives some
additional phase ‘boost’. Fortunately, there is an opposite
trend in mobile applications to keep the output capacitor as
small as possible.
Automatic Operation Mode Control
The mode control circuit changes the converter’s mode of
operation depending on the level of the load current. At
nominal current the converter operates in a fixed frequency
PWM mode. When the load current drops lower than the
critical value, inductor current becomes discontinuous and
the operation mode is changed to hysteretic.
The mode control circuit consists of a flip-flop which provides
HYST and NORMAL signals. These signals inhibit normal
PWM operation and activate hysteretic comparator and
diode emulation mode of the synchronous MOSFET.
The inputs of the flip-flop are controlled by the outputs of two
delay circuits that constantly monitor output of the phase
node comparator. High level on the comparator output
during PWM cycle is associated with continuous mode of
operation. The low level -- corresponds to the discontinuous
mode of operation. When the low level on the comparator
output is detected eight times in a row, the mode control flip-
flop is set and converter is commanded to operate in the
MODULATOR
G
EA
= 18DB
EA
F
CONVERTER
PO
FIGURE 6.
F
10
Z
R1
F
C
G
EA
TYPE 2 EA
= 14dB
R2
C2
C1
F
P
IPM6210A
hysteretic mode. If during this pulse counting process the
comparator's output happens to be high, the counter of the
delay circuit will be reset and circuit will continue to monitor
for eight low-level pulses in a row, as shown in Figure 7.
The circuit which restores normal PWM operation mode works
in the same way and is looking for eight in a row high-level
pulses on the comparator’s output. If during this counting
process the comparator’s output happens to be low, the
counter will be reset and the mode control flip-flop will not
change the state. The operation mode will only be changed
when eight pulses in a row fill the counter, see Figure 8. This
technique prevents jitter and chatter of the operation mode
control logic at the load levels close to the critical.
Hysteretic Operation
When discontinuous inductor current is detected, the mode
control logic changes the way the signals in the chip are
processed by entering hysteretic mode. The comparator and
the error amplifier that provided control in the PWM mode
are inhibited, and the hysteretic comparator is now activated.
Changes are also made to the gate logic. The synchronous
rectifier MOSFET is now controlled in diode emulation mode,
hence conduction in the second quadrant is prohibited.
The converter output voltage is applied to the negative input of
the hysteretic comparator. The voltage on the reference input of
the hysteretic comparator is the DAC output voltage with a
V
I
PHASE
MODE
OF
OPERATION
MODE
OF
OPERATION
IND
PHASE
COMP
COMP
OUT
V
OUT
I
IND
FIGURE 7. PWM TO HYSTERETIC TRANSITION
FIGURE 8. HYSTERETIC TO PWM TRANSITION
1 2 3 4 5 6 7 8
HYSTERETIC
PWM
1
2 3 4 5
6 7 8
HYSTERETIC
PWM
t
t
t
t
t
t
t
t