hsp50016 Intersil Corporation, hsp50016 Datasheet
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hsp50016
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hsp50016 Summary of contents
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... In mode three, the user may provide an external clock through the 96 pin input connector. The HSP50016-EV was built into a 3U Euro-Card form factor with dual 96 Pin Input/Output connectors. The I/O connectors conform to the VME J2/P2 Connector Standard. HSP50016 Evaluation Platform ...
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... Line Interface (see Command Line Interface Section) to initialize the evaluation board, clock a data vector through the HSP50016-EV, and store the output to a file. The output file is then compared, using the DOS command COMP file containing a set of vectors generated by a properly functioning board. If the TEST_IN.DAT and TEST.OUT.DAT fi ...
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... TEST_OUT.DAT file was created. IQSTB SELECT 1 QOUT SELECT JP20 FIGURE 1. LAYOUT OF HSP50016-EV SHOWING DEFAULT JUMPER CONFIGURATION 3-3 HSP50016-EV NOTE: if the operating system precedes DOS 6.0, the user should answer NO to the COMP command prompt to compare additional files. DOS Version 6.0 and above use a different fi ...
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... DDC. The Loop Count allows the user to simulate long data streams by repeatedly sending the same input file. If file based output is specified, the software reads the data on the I and Q outputs of the HSP50016 and stores the data in the specified file. The software automatically reads the ...
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... CLK setting. The format for the TAP input and output files is given in Appendix B. HSP50016 Data Inputs The data window to the left of the HSP50016 icon is used to specify hexadecimal values which drive the DDC's data inputs DATA0-15. Data is entered into this window in hexadecimal format starting with the most signifi ...
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... If jumpers are inserted as shown in Figure 3, the CLK_OUT pin of the P2 connector drives the clock buffer which in turn drives the clock input of the HSP50016. The jumper inserted between JP16 pin 2 and JP17 pin 2 allows the CLKIN pin to be driven by the buffer output. NOTE: The jumper placement shown in Figure 2 is the standard confi ...
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... FIGURE 4. CONTROL PANEL SCREEN AS DISPLAYED ON PC CLOCK SELECT MANUAL CLK AVAILABLE PRINTER PORTS PORT CLK OSC. CLK EXTERNAL CLK CONTROL SIGNALS 1 RESET# 0 IQSTRT# CONTROL WORDS CURRENT PORT SELECTION CURRENT HSP50016-EV ADDRESS : 0 000000000 1 200000001 2 000000000 3 000000000 4 00000006E 5 00D002100 6 000000000 7 000000002 F1 - HELP F2 - START CLOCK F3 - START JTAG FIGURE 5 ...
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... Argument #3. Setting the update bit = 1 updates the configuration of the DDC; update bit = 0 only modifies the control word. Reads one of the HSP50016’s control words to the screen. If Argument #1 is omitted, all control words are displayed. Loads the evaluation board’s control register with a 16-bit hexadecimal value. ...
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... Hardware Overview The HSP50016-EV was designed to facilitate prototyping with the HSP50016 Digital Down Converter. It can be used in a stand alone mode, in conjunction with other Intersil evaluation boards inserted into a card cage and operate as a part of a larger system. The following description of the board references both the Block Diagram in Figure 6 and the Schematic Diagrams, which are included at the back of this manual ...
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... N.C. 22 GND GND 23 GND N.C. 24 GND N.C. 25 GND N.C. 26 PCD0 N.C. 27 PCD2 N.C. 28 PCD4 N.C. 29 PCD6 N.C. 30 PCWR0 N.C. 31 PCWR1 GND 32 PCRD1 V CC 3-10 HSP50016-EV TABLE 4. PIN ASSIGNMENTS FOR 96 PIN OUTPUT CONNECTOR P2 ROW C SIGNAL PIN MNEMONIC NUMBER GND 1 DIN1 2 DIN3 3 DIN5 4 DIN7 5 DIN8 6 DIN10 7 DIN12 8 DIN14 9 GND 10 N.C. 11 N.C. 12 N.C. 13 N.C. 14 GND 15 N ...
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... ADDRESS D7 D6 D5-3 Register Structure The HSP50016-EV provides a set of registers which may be used as a source for DDC input and control. They can be loaded from either the parallel port or from the P1 connector. Down Loading Data via Parallel Port Interface The control and input registers are down loaded from the series of single byte writes to the to the Parallel Port Interface ...
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... JP5 (see Configuration Jumper Field Section). The DIN0-15 pins on P1 are then used to drive the input pins of the HSP50016. If all 16 pins are not used, then the DIN bus should be loaded starting from bit 15 down. When JP5 is not installed, all data input pins must either be driven by an external data source or grounded to avoid damage to the board ...
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... MSB first, although the circuit will work just as well in LSB first mode. HSP50016-EV Limited Warranty Intersil warrants the HSP50016- free of defects in material and workmanship under normal use for a period of ninety (90) days. Intersil also warrants that the HSP50016- EV User's Manual is substantially complete and contains all ...
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... Appendix A Data File Structures The Input/Output data files used by the HSP50016-EV Control Panel and Command Line Interface Software contain data samples. The data files consist of a seven line header followed by the data itself. The Header Section must follow this format: Line 1: ...
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... HSP50016-EV 3-15 ...
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Schematic (Continued) I OUT QOUT I QSTB I QCLK TDO TDO TDO SEL0 SEL0 SEL1 SEL1 SEL2 SEL2 I OUT I OUT I QCLK I QCLK I QSTB I QSTB SRRST# SRRST# SROE# SROE# J P20 1 2 QOUT 3 ...
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Schematic (Continued) CKOUT CKOUT VCC QO0 2 2 QO2 3 3 QO4 4 4 QO6 QO9 7 7 QO1 QO1 QO1 ...
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Schematic (Continued) U15C 9 10 74ACT86 VCC TCK PCW R1 6 TDI . TRST JP14 U15A 1 1 DDC CLK INV 2 2 SHADING ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 3-19 HSP50016-EV EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd ...