hy27uh088g Hynix Semiconductor, hy27uh088g Datasheet
hy27uh088g
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hy27uh088g Summary of contents
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... Correct Address Cycle Map. Rev 0.7 / Feb. 2006 History tWH tWP tWC 8,196 8,192 LI, LO HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Draft Date Remark May. 13. 2005 Preliminary May. 23. 2005 Preliminary Jun. 13. 2005 Preliminary Jun. 14. 2005 Preliminary Sep. 16. 2005 Preliminary 1 ...
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... Rev 0.7 / Feb. 2006 History tWP tWH 35ns 20ns 25ns 15ns CC2 CC3 LI LO Typ Max Max 30 30 ± 20 ± ± 40 ± 40 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash -Continued- Draft Date Remark Sep. 16. 2005 Preliminary Oct. 05. 2005 Preliminary Dec. 09. 2005 Feb. 14. 2006 2 ...
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... Cost effective solutions for mass storage applications NAND INTERFACE - x8 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = 2.7 to 3.6V : HY27UH088G(2/D)M Memory Cell Array = (2K+ 64) Bytes x 64 Pages x 8,192 Blocks PAGE SIZE - x8 device : ( spare) Bytes : HY27UH088G(2/D)M BLOCK SIZE ...
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... SUMMARY DESCRIPTION The HYNIX HY27UH088G(2/D)M series is a 1Gx8bit with spare 32Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently possible to preserve valid data while old data is erased ...
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... CLE ALE R/B Vcc Vss NC PRE Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground ...
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... Figure 2. 48TSOP1 Contactions, x8 Device Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 6 ...
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... Figure 3. 52-ULGA Contactions, x8 Device, Dual interface Rev 0.7 / Feb. 2006 (Top view through package) HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 7 ...
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... A 0.1uF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Description Table 2: Pin Description ...
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... D0h 70h - 85h - 05h E0h 00h 31h 34h - 2Ah - 2Ch - 23h - 24h - 7Ah - Table 4: Command Set HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash IO4 IO5 IO6 (1) (1) ( A16 A17 A18 A24 A25 A26 (1) (1) ( ...
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... 0V/Vcc Table 5: Mode Selection HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash MODE Command Input Read Mode Address Input(5 cycles) Command Input Write Mode Address Input(5 cycles) Data Input Sequential Read and Data Output During Read (Busy) During Program (Busy) ...
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... Write Protect pin is not latched by Write Enable to ensure the pro- tection even during the power up. 2.6 Standby. In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 11 ...
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... The command register remains in Read Sta- tus command mode until another valid command is written to the command register. Figure 12 details the sequence. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 1 ...
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... Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. See figure 8 for details of the Read Status operation. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 13 ...
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... Program time for the last page+ Program time for the ( last -1 )th page - (Program command cycle time + Last page data loading time) Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 14 ...
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... If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command. Random data output is not available in cache read. Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 15 ...
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... Unlocked blocks can be locked by using the Lock block command, and a lock block’s status can be changed to unlock or lock-tight using the appropriate commands - On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY) Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 16 ...
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... Power-On Auto Read mode is available only on 3.3V device. Alternatively the device can support an automatic cache read download, with all same functionalities stated just above for auto-read. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 17 ...
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... Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. Rev 0.7 / Feb. 2006 Min N 8032 VB Table 6: Valid Blocks Number Parameter Table 7: Absolute maximum ratings HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Typ Max 8192 Value 3. - ...
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... Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Figure 4: Block Diagram 19 ...
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... Vcc (max Vcc (max) LO OUT =-400uA =2.1mA =0.4V OL (R/B) Table 9: AC Conditions HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 3.3Volt Min Typ Max - 1 200 - - ± ± 40 0.8xVcc - Vcc+0.3 -0.3 - 0.2xVcc 2 ...
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... Dummy Busy Time for Cache Read Dummy Busy Time for the Lock or Lock-tight Block Number of partial Program Cycles in the same page Block Erase Time Table 11: Program / Erase / Read Characteristics Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Symbol Test Condition C V ...
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... If tCS is less than 10ns tWP must be minimum 35ns, ohterwise, tWP may be minimum 25ns. 4. Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High. tCS=min. 40ns after Autosleep 5. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 3.3Volt Symbol Min t ...
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... Table 13: Status Register Coding DESCRIPTION Manufacturer Code Device Identifier Page Size, Block Size, Spare Size, Organization Table 14: Device Identifier Coding HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Cache CODING Read Pass: ‘0’ Fail: ‘1’ Pass: ‘0’ Fail: ‘1’ ...
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... HY27UH088GDM 3.3V Rev 0.7 / Feb. 2006 IO7 IO6 Bus Width Manufacture Code x8 ADh x8 ADh Table 16: Read ID Data Table HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash IO5-4 IO3 IO2 Device 3rd code Code D3h don’t care Dch don’ ...
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... Rev 0.7 / Feb. 2006 Table 17: Lock Status Code Figure 5: Command Latch Cycle HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 25 ...
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... Rev 0.7 / Feb. 2006 Figure 6: Address Latch Cycle HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 26 ...
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... Figure 8: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Figure 7. Input Data Latch Cycle 27 ...
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... Figure 10: Read1 Operation (Read One Page) Rev 0.7 / Feb. 2006 Figure 9: Status Read Cycle HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 28 ...
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... Figure 11: Read1 Operation intercepted by CE Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 29 ...
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... Rev 0.7 / Feb. 2006 Figure 12 : Random Data output HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 30 ...
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... Rev 0.7 / Feb. 2006 Figure 13: Page Program Operation HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 31 ...
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... Rev 0.7 / Feb. 2006 Figure 14 : Random Data In HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 32 ...
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... Rev 0.7 / Feb. 2006 Figure 15 : Copy Back Program HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 33 ...
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... Rev 0.7 / Feb. 2006 8Gbit (1Gx8bit) NAND Flash Figure 16 : Cache Program HY27UH088G(2/D)M Series 34 ...
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... Figure 17: Block Erase Operation (Erase One Block) Rev 0.7 / Feb. 2006 Figure 18: Read ID Operation HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 35 ...
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... Figure 19: start address at page start :after 1st latency uninterrupted data flow Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 36 ...
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... Figure 20: exit from cache read in 5us when device internally is reading Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 37 ...
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... So possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND Flash to make CE don’t care read operation was disabling of the automatic sequential read function. Figure 21: Program Operation with CE don’t-care. Figure 22: Read Operation with CE don’t-care. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 38 ...
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... Rev 0.7 / Feb. 2006 Figure 22: Lock Command Figure 23: Unlock Command Sequence HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 39 ...
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... Rev 0.7 / Feb. 2006 Figure 24: Lock Tight Command Figure 25: Lock Status Read Timing HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 40 ...
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... Rev 0.7 / Feb. 2006 Figure 26: Automatic Read at Power On Figure 27: Reset Operation HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 41 ...
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... Rev 0.7 / Feb. 2006 Figure 28: Power On/Off Timing VTH = 2.5 Volt for 3.3 Volt Supply devices HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 42 ...
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... Figure 29: Ready/Busy Pin electrical specifications Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 43 ...
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... Figure 31: page programming within a block Rev 0.7 / Feb. 2006 Figure 30: Lock/Unlock FSM Flow Cart HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 44 ...
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... Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation. Operation Erase Program Read Figure 32: Bad Block Management Flowchart Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Recommended Procedure Block Replacement Block Replacement or ECC Table 18: Block Failure ECC ...
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... Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 33~36) Rev 0.7 / Feb. 2006 Figure 33: Enable Programming Figure 34: Disable Programming HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 46 ...
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... Rev 0.7 / Feb. 2006 8Gbit (1Gx8bit) NAND Flash Figure 35: Enable Erasing Figure 36: Disable Erasing HY27UH088G(2/D)M Series 47 ...
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... To do this the internal address register can store addresses(512Mbyte addressing field) and basing on the 2 MSB pattern each device inside the package can decide if remain active (1 over “hang up” the connection entering the Stand-By. Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 48 ...
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... Table 19: 48pin-TSOP1 20mm, Package Mechanical Data Rev 0.7 / Feb. 2006 millimeters Min Typ 0.050 0.980 0.170 0.100 11.910 12.000 19.900 20.000 18.300 18.400 0.500 0.500 0 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Max 1.200 0.150 1.030 0.250 0.200 0.100 12.120 20.100 18.500 0.680 5 49 ...
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... Figure 38. 52-TLGA 17mm, Package Outline Symbol CP1 CP2 Table 20: 52-TLGA 17mm, Package Mechanical Data Rev 0.7 / Feb. 2006 (Top view through package) Min 16.90 11.90 0.90 0.65 0.95 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash millimeters Typ Max 17.00 17.10 13.00 12.00 12.00 12.10 10.00 6.00 1.00 1.50 2.00 1.00 1.00 0.95 1.00 0.70 0.75 1.00 1.05 50 ...
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... C (0 ℃ ℃ (-2 5 ℃ ℃ (-3 0 ℃ ℃ ), I(-4 0 ℃ ℃ ( Ite -fix e d Ite m HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash ...
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... WP at VIL during power-on/off. For the device to operate stably highly recommended to operate the device as shown Fig.38. Rev 0.7 / Feb. 2006 Figure 38: Power-on/off sequence HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 52 ...
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... CE to VIL level. Typically, consecutive operation is executable right after deactivating the automatic sleep mode, while tCS of 40ns is required prior to following operation as shown in Fig.39. Figure 39: tCS setting when deactivating the auto sleep mode Rev 0.7 / Feb. 2006 HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash 53 ...