gs9015a Gennum Corporation, gs9015a Datasheet - Page 12

• Manufacturer Part Number: gs9015a
• Description: Serial Digital Reclocker Corporation
• Manufacturer: Gennum Corporation

520 - 99 - 05
All resistors in ohms,
all capacitors in microfarads,
all inductors in henries unless otherwise stated.
Application Note - PCB Layout
Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout
Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B Deserializer
Evaluation Board”
The use of a star grounding technique is required for the loop filter components of the GS9005A/15A.
Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and
the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed
when a microstrip trace runs across a break in the ground plane.
The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.
VCC
0.1
SERIAL
DIGITAL
INPUT
STAR
ROUTED
5.6p
10
11
5
6
7
8
9
10n
DDI
DDI
VCC1
VEE1
VEE1
ƒ/2
VEE3
(1) To reduce board space, the two anti-series 6.8 F capacitors (connected across pins 2 and 3 of
the GS9010A) may be replaced with a 1.0 F non-polarized capacitor provided that:
(2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to
(1)
(a) the 0.68 F capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
(b) the GS9005A /15A Loop Filter Capacitor is 10 nF.
a maximum of 300 Mbps.
12 13 14 15 16 17 18
VCC
910
4
0.33 F capacitor and
6.8
6.8
GS9015A
0.1
3
(1)
0.1
1.2k
+
+
2
1
28 27 26
1.2k
120
VCC
3.3n
SDO
SDO
SCO
SCO
SS1
SS0
CD
VCC
SWF
25
24
23
22
21
20
19
0.1
1
2
3
4
5
6
7
8
VCC
0.1
P/N
OUT
IN-
COMP
LF
ƒ/2
V CC
SWF
GS9010A
Fig. 17 Typical Application Circuit
10
HSYNC
FVCAP
STDT
GND
V CC
OSC
DLY
VCC
+5V
GND
CD
+
16
15
14
13
12
11
10
9
100
390
390
100
100
390
390
100
DVCC
+5V
DGND
VCC
+
10
50k
VCC
(2)
0.1
VCC
82n
DVCC
10
11
5
6
7
8
9
180n
12
DGND
SWF
SDI
SDI
SCI
SCI
SS1
SS0
SST
0.1
DGND
DVCC
100
12 13 14 15 16
68k
4
VCC
or GS9000S
GS9000B
3
DGND
3.3k
100k
DGND
0.68
2
(1)
22n
1
100 100
(3)
100
28 27 26
17
100
PD7
PD6
PD5
PD4
PD3
PD2
PD1
18
DGND
0.1
DGND
25
24
23
22
21
20
19
DVCC
100
100
100
100
100
100
100
STANDARD TRUTH TABLE
ƒ/2
0
0
1
1
P/N
0
1
0
1
STANDARD
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
SYNC WARNING FLAG
HSYNC OUTPUT
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE