gs9005a Gennum Corporation, gs9005a Datasheet
gs9005a
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gs9005a Summary of contents
Page 1
... Standards Select input pins. An additional feature is the Signal Strength Indicator output which provides a 0. analog output relative to V indicating the amount of equalization being applied to the signal. The GS9005A is packaged pin PLCC operating from a single + volt supply. SPECIAL NOTE: R TEMPERATURE reduced temperature range of T ...
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... V IL MAX Carrier Detect V CDL Output Voltage V CDH Signal Strength V SS Indicator Output Direct Digital Input V DDI Levels (5, 6) GS9005A RECEIVER AC ELECTRICAL CHARACTERISTICS 100 PARAMETER SYMBOL Serial Data Bit Rate BR SDO Serial Clock Frequency ƒ ...
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... GS9005A Re - clocking Receiver - Detailed Device Description The GS9005A Reclocking Receiver is a bipolar integrated circuit containing a built-in cable equalizer and circuitry necessary to re-clock and regenerate the NRZI serial data stream. Packaged pin PLCC, the receiver operates from a single five volt supply at data rates in excess of 400 Mb/s. ...
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... SERIAL DATA OUT (SD0) SERIAL 50% CLOCK OUT (SCK) Fig.1 Waveforms GS9005 & GS9005A PIN DESCRIPTIONS PIN NO. SYMBOL TYPE 1 A/D Input Analog/Digital Select. TTL compatible input used to select the input signal source. A logic HIGH routes the Equalizer inputs (pins 8 and 9) to the PLL and a logic LOW routes the Direct Digital inputs (pins 5 and 6) to the PLL ...
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... GS9005 & GS9005A PIN DESCRIPTIONS cont. PIN NO SYMBOL TYPE 18 V Power Supply. Most positive power supply connection. (VCO, MUX, standards select). CC3 19 CD Output Carrier Detect. Open collector output which goes HIGH when a signal is present at either the Serial Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S in the Automatic Standards Select Mode to disable the 2 bit standard select counter ...
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INPUT / OUTPUT CIRCUITS cont. Pin 13 R VCO 0 Pin 14 R VCO 1 Pin 15 R VCO 2 Pin 17 R VCO 3 520 - VCO (1.9 - 2.4V) 400 400 400 400 Fig. ...
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INPUT / OUTPUT CIRCUITS cont. SSI Pin 28 5k AGC CAP Pin 0. SDI Pin 8 SDI Pin 9 Fig. 6 Pins 28 and OEM ...
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TYPICAL PERFORMANCE CURVES ( 500 450 400 350 300 250 ƒ/2 OFF 200 ƒ/2 ON 150 100 FREQUENCY SETTING RESISTANCE (k ) Fig. 11 Clock ...
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... TEST SETUP Figure 16 shows a typical circuit for the GS9005A using a +5 volt supply. The four 0.1 F decoupling capacitors must be placed as close as possible to the corresponding V The loop voltage can be conveniently measured across the 10nF capacitor in the loop filter. Tuning procedures are described in the Temperature Compensation Section (page 11) ...
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... VCO Frequency Setting Resistors There are two modes of VCO operation available in the GS9005A. When the ƒ/2 ENABLE (pin 10) is LOW, any of the four VCO frequency setting resistors, RVCO0 through RVCO3 (pins 13, 14, 15 and 17) may be used for any data rate from 100 Mb/s to over 400 Mb/s ...
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... VCO2 VCO3 ance drops, the loop gain increases. Applications Circuit 1k Figure 20 shows an application of the GS9005A in an adjustment free, multi-standard serial to parallel convertor. This circuit uses the GS9010A Automatic Tuning Sub- 0.1µF system IC and a GS9000B or GS9000S Decoder IC. The GS9005A may be replaced with a GS9015A Reclocker IC 1N914 if cable equalization is not required ...
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... The use of a star grounding technique is required for the loop filter components of the GS9005A/15A. Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed when a microstrip trace runs across a break in the ground plane ...