gs9023-cfy ETC-unknow, gs9023-cfy Datasheet - Page 22

• Manufacturer Part Number: gs9023-cfy
• Description: Embedded Audio Codec
• Manufacturer: ETC-unknow

MULTIPLEX AND DEMULTIPLEX MODES
Delay of Video and Audio
The GS9023 can be configured for various audio sample
delays with respect to the video signal. The audio sample
delay is selected in “BUFSEL[1:0]” of Host Interface
Register #6h. Table 13 lists the various audio sample
delays.
TABLE 13: Audio Video Delay
Host Interface
The Host Interface Registers allow for device configuration
and provide status information. The GS9023 contains
sixteen internal registers that are accessible through the
Host Interface. Based on the mode of operation the
registers have different functionality. In Multiplex Mode the
registers are defined in Table 14 and in Demultiplex Mode
the registers are defined in Table 15.
The asynchronous Host Interface consists of a 4 bit address
bus (ADDR[3:0]), 8 bit data bus (DATA[7:0]), read enable
(RE), write enable (WE) and chip select (CS). The Host
Interface access is independent of the PCLK or ACLK
inputs. Read and write cycle timing is detailed in Figure 16.
In a read cycle, CS is driven LOW t
address. RE is then driven LOW after t
minimum of t
register contents are output on the data bus. After a
minimum of t
cycle.
Similarly, in a write cycle, CS is driven LOW t
after a valid address. WE is then driven low after t
seconds for a minimum of t
present for a minimum of t
HIGH again. After a minimum of t
HIGH to end the cycle.
Reset
Reset timing is detailed in Figure 17. Setting the RESET pin
to LOW for a period of t
outputs LOW and re-initializes the internal control circuitry
including returning all Host Interface Register values to their
original default values. The RESET pin can be used for
synchronizing multiple devices.
GENNUM CORPORATION
NOTE: When the video signal is in D2 format, the delay is fixed at 70 samples (1416 us).
“BUFSEL[1:0]”
0
1
2
RD
RDH
seconds. After t
seconds, CS is driven HIGH to end the
(26 Sample -
(70 Sample)
(20 Sample)
Default)
RESET
MODE
DS
WD
seconds before WE is driven
seconds. Valid data must be
seconds forces the audio
GQV
WDH
AS
seconds, the address
seconds, CS is driven
seconds after a valid
ACS
MULTIPLEX (us)
seconds for a
AS
875
250
187
seconds
ACS
22
DEMULTIPLEX
Non-Standard Sample Distributions
Gennum Corporation has made every effort to maximize
compatibility of the GS9023 with other Embedded Audio
data
implementations (i.e. non-standard sample distributions)
Gennum cannot guarantee compatibility with all Embedded
Audio data streams.
Interconnection with GS9032 or GS7005
The user should pay special attention when laying out the
GS9023 to operate with the GS9032 or GS7005. The MSB
to LSB convention is consistent between the GS9023 and
GS9022 but reversed with respect to the GS9032 or
GS7005. Layout complexity can be minimized by placing
the GS9023 and the GS9032 or GS7005 on opposite sides
of the printed circuit board (PCB).
(us)
541
312
250
streams.
MULTIPLEX/DEMULTIPLEX
Unfortunately,
CONNECTION (us)
1416
563
437
due
to
variations
522 - 45 - 05
in