gs9023-cfy ETC-unknow, gs9023-cfy Datasheet - Page 18

• Manufacturer Part Number: gs9023-cfy
• Description: Embedded Audio Codec
• Manufacturer: ETC-unknow

DEMULTIPLEX MODE
Video Clock Input
A master video clock must be supplied to the PCLK pin
corresponding to the selected video signal. The supported
video input standards and corresponding clock frequencies
are listed in Table 1.
Video Data Input
The video data DIN[9:0] is clocked in to the GS9023 on the
rising edge of PCLK. The video clock frequency must
correspond to the video input standard selected. This can
be done with the VM[2:0] and TRS input pins or selected
via the “VSEL” bit of Host Interface Register #0h. When
“VSEL” is set HIGH, the video input standard is selected by
“VMOD[2:0]” and “D2_TRS” in Host Interface Register #0h.
The supported video input standards are listed in Table 1.
After the user has specified the video input standard via the
VM[2:0] and TRS pins or in Host Interface Register #0h, the
GS9023 performs video standard detection to verify that the
input video stream corresponds to the selected standard.
When the selected video input standard is verified, the
“VXST” bit of Host Interface Register #0h is set HIGH. The
GS9023 then performs a ‘lock’ procedure, as selected by
the “ACTSEL” bit of Host Interface Register #4h, to
determine if the audio is synchronous to the video. When
“ACTSEL” is LOW, the GS9023 counts the number of audio
samples present in a frame or multiple frames, depending
on the video standard selected. ‘Lock’ is achieved if the
required number of samples are detected for 48kHz
synchronous audio. When “ACTSEL” is HIGH, the GS9023
‘locks’ by detecting the presence of an audio control packet
corresponding to the DID configured in “ACID[3:0]” of Host
GENNUM CORPORATION
Empty
Video signal after GS9023 Removal of Audio Group 1 & Extended
Audio Group 1 (ANCI = HIGH or "VSEL" and "ADEL" = HIGH)
Video signal before GS9023
Fig.10
18
Interface Register #4h and occurring at the expected line
and position as listed in Table 6. If the video signal does not
contain audio control packets, ‘lock’ will not occur. Once
‘lock’ is achieved the LOCK output pin and the “LOCK” bit
of Host Interface Register #0h are set HIGH and audio
demultiplexing begins. The LOCK output pin and the
“LOCK” bit stay active regardless of the number of samples
in the video stream after ‘lock’ is achieved. The GS9023
drops out of ‘lock’ when there are no more packets
detected in the video stream.
Video Data Output
The video signal is output at the DOUT[9:0] pins. The video
signal is synchronized to the rising edge of PCLK. The
GS9023 is capable of removing audio, extended audio,
arbitrary and audio control packets from the video stream.
To remove packets, the user must set the ANCI pin HIGH or
set the “VSEL” and “ADEL” bits of Host Interface Register
#0h HIGH. The GS9023 then removes each packet having a
DID corresponding to either the audio DID, the extended
audio DID or the arbitrary data DID stored in the Host
Interface Registers from the video stream. See Figure 10 .
NOTE:
unchanged in the Demultiplex Mode. If any audio, extended
audio, arbitrary or audio control packets are deleted by the
GS9023, the EDH CRC words become invalid.
When the ANCI pin or “ADEL” bit is LOW, all ancillary data
packets remain in the video signal. See Figure 11 .
TRS can also be removed from a 525/625 D2 video signal
when the TRS pin is set HIGH or the “VSEL” and “D2_TRS”
bits of Host Interface Register #0h are set HIGH.
The
GS9023
Empty
Empty
passes EDH
packets
522 - 45 - 05
through