as7c34098a Alliance Memory, Inc, as7c34098a Datasheet - Page 2

• Manufacturer Part Number: as7c34098a
• Description: 3.3 V 256 K ? 16 Cmos Sram
• Manufacturer: Alliance Memory, Inc

Functional description
The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input
pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is
available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2.
Truth table
8/17/04,v. 2.1
Key: X = Don’t care, L = Low, H = High.
CE
H
L
L
L
L
Absolute maximum ratings
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
DC current into outputs (low)
WE
X
H
X
H
L
CC
relative to GND
Parameter
OE
X
H
X
L
X
CC
applied
AA
, t
LB
X
X
H
L
H
L
L
H
L
RC
Alliance Memory Inc
, t
WC
) of 10/12/15/20 ns with output enable access times (t
Symbol
I
T
T
V
V
OUT
P
UB
bias
X
X
H
H
L
L
H
L
L
stg
D
t1
t2
®
I/O1–I/O8
High Z
High Z
High Z
High Z
D
D
–0.50
–0.50
D
D
Min
OUT
OUT
–65
–55
IN
IN
–
–
I/O9–I/O16
High Z
High Z
High Z
High Z
D
D
V
D
D
OUT
OUT
IN
IN
CC
+150
+125
Max
+5.0
±20
1.5
+0.50
OE
Output disable (I
AS7C34098A
Standby (I
) of 4/5/6/7 ns are
P. 2 of 10
Unit
Write (I
Read (I
mA
°C
°C
W
V
V
Mode
SB
CC
CC
, I
)
)
SB1
CC
)
)