as7c33512pfd18a ETC-unknow, as7c33512pfd18a Datasheet - Page 17

• Manufacturer Part Number: as7c33512pfd18a
• Manufacturer: ETC-unknow

AC test conditions
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
5) t
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to
8) Chip select refers to
12/1/04; v.1.3
HZOE
CH
+3.0V
• Output load: see Figure B, except for t
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
GND
measured HIGH above V
Figure A: Input waveform
is less than t
10%
90%
GWE, BWE, BW[a,b]
LZOE
CE0, CE1, CE2
and t
90%
HZC
IH
10%
and t
is less than t
.
.
CL
measured as LOW below V
D
OUT
LZC
LZC
at any given temperature and voltage.
Figure B: Output load (A)
, t
Alliance Semiconductor
LZOE
Z
0
= 50Ω
, t
HZOE
IL
, t
HZC
50Ω
30 pF*
, see Figure C.
V
®
L
for 3.3V I/O;
= V
for 2.5V I/O
= 1.5V
DDQ
/2
353Ω / 1538Ω
D
OUT
Figure C: Output load (B)
AS7C33512PFD18A
Thevenin equivalent:
319Ω / 1667Ω
5 pF*
GND
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
*including scope
and jig capacitance
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