as7c33512pfd18a ETC-unknow, as7c33512pfd18a Datasheet
as7c33512pfd18a
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as7c33512pfd18a Summary of contents
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... Byte Write registers CLK D Q Enable register CE CLK D Q Enable Power delay down register CLK –166 6 166 3.5 475 130 30 Alliance Semiconductor AS7C33512PFD18A DDQ 512K × 18 Memory 19 array Input Output registers registers CLK CLK 18 DQ[a,b] –133 7.5 133 4 425 100 Copyright © ...
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... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C33512PFD18A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
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... DQb5 DDQ V 21 SSQ DQb6 22 DQb7 23 DQpb SSQ V 27 DDQ 12/1/04; v.1.3 ® TQFP 14 × 20mm Alliance Semiconductor AS7C33512PFD18A DDQ V 76 SSQ NC 75 DQpa 74 DQa7 73 DQa6 SSQ V 70 DDQ DQa5 69 DQa4 68 VSS ...
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... WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH). • Master chip select CE0 blocks ADSP, but not ADSC. The AS7C33512PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging. ...
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... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE PUS MODE. 12/1/04; v.1.3 ® Description are synchronous to this clock. LBO or left floating, device follows Interleaved Burst DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ ZZI Alliance Semiconductor AS7C33512PFD18A . The duration of SB2 ...
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... High Starting Address First Increment Second Increment Third Increment Alliance Semiconductor AS7C33512PFD18A Linear burst address (LBO = ...
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... H H Current External Next Next Current Current Alliance Semiconductor AS7C33512PFD18A CLK Operation Deselect Hi− Deselect Hi− Deselect Hi− Deselect Hi− Deselect Hi− Begin read Begin read Hi−Z ...
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... D I – OUT T –65 stg T –65 bias Symbol Min V 3.135 DD V 3.135 DDQ Vss 0 Symbol Min V 3.135 DD V 2.375 DDQ Vss 0 Alliance Semiconductor AS7C33512PFD18A Max Unit +4 0 0.5 V DDQ 1 °C +150 °C +135 Nominal Max Unit 3.3 3.465 V 3.3 3.465 ...
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... Deselected < 0.2V, ≤ 0.2V or ≥ V all ≥ V Deselected Max ≤ ≥ V all CE0 < CE1 > CE2 < mA, ZZ < OUT Alliance Semiconductor AS7C33512PFD18A Min Max -2 2 < DDQ * +0.3 DDQ ** -0.3 0 ...
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... 1.5 CSS 0.5 CSH t 1.5 ADVS t 1.5 ADSPS t 1.5 ADSCS t 0.5 ADVH t 0.5 ADSPH t 0.5 ADSCH Alliance Semiconductor AS7C33512PFD18A –133 Max Min Max Unit Notes 166 – 133 MHz – 7.5 – ns 3.5 - 4.0 ns 3.5 – 4.0 ns – 0 – ns 2,3,4 – 1.5 – – 0 – ns 2,3,4 3.5 – 4.0 ns 2,3,4 3.5 – ...
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... WH t 0.7 CSH t 1.7 ADVS t 1.7 ADSPS t 1.7 ADSCS t 0.7 ADVH t 0.7 ADSPH t 0.7 ADSCH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33512PFD18A –133 Max Min Max Unit Notes 166 – 133 MHz – 7.5 – ns 4.0 - 4.5 ns 3.5 – 4.0 ns – 0 – ns 2,3,4 – 1.5 – – 0 – ns 2,3,4 3 ...
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... ADV inserts wait states HZOE t OH Q(A2) Q(A2Ý01) Q(A2Ý10) Burst Burst Suspend Burst Read Read Read Read Q(A 2Ý01 ) Q(A 2Ý10 ) Q(A 2Ý10 ) Q(A 2Ý11 ) Alliance Semiconductor AS7C33512PFD18A Undefined t HZC Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Read Burst Burst Burst Q(A3) Read Read Read * DSEL Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...
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... ADSC LOADS NEW ADDRESS A2 ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) ADV Suspend Read ADV Suspend Burst Write Q(A2) Burst Write Write D Write D(A 2Ý01 ) D(A 2Ý01 ) D(A 2Ý10 ) Alliance Semiconductor AS7C33512PFD18A t t ADSCS ADSCH ADVS ADVH D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) ADV ADV ...
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... ADVH ADVS D(A2 HZOE LZOE Q(A1) Suspend Read Suspend Read Read Q(A2) Write Q(A3) Q(A1) D Alliance Semiconductor AS7C33512PFD18A Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) ADV ADV ADV Burst Burst Burst Read Read Read Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...
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... GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Q(A1) Dout Din READ READ READ Q(A1) Q(A2) Q(A3) 12/1/04; v.1.3 ® t CYC HZOE Q(A2) Q(A3) Q(A4 D(A5) D(A6) READ WRITE WRITE D(A6) Q(A4) D(A5) Alliance Semiconductor AS7C33512PFD18A LZOE OH Q(A8) Q(A9) DH D(A7) READ WRITE READ Q(A9) D(A7) Q(A8 ...
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... Q(A1 Setup Cycle I supply S READ USPEND READ Q(A1) Q(A1) 12/1/04; v.1.3 ® HZC t PUS PDS ZZ Recovery Cycle t ZZI t RZZI I SB2 Sleep State Alliance Semiconductor AS7C33512PFD18A t CYC D(A2) t HZOE D(A2(Ý01)) Normal Operation Mode READ USPEND Q(A2) WRITE TINUE WRITE D(A2) D(A2 Ý01 ...
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... L for 3.3V I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC IL Alliance Semiconductor AS7C33512PFD18A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω / 1667Ω D OUT 5 pF* 353Ω / 1538Ω GND *including scope and jig capacitance Figure C: Output load (B) ...
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... Package Dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14. 19.90 20.10 e 0.65 nominal Hd 15.90 16.10 He 21.90 22.10 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 12/1/04; v.1.3 ® Alliance Semiconductor AS7C33512PFD18A α ...
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... Clock speed (MHz) 9. Package type: TQ=TQFP 10. Operating temperature: C=Commercial (0° 70° C); I=Industrial (-40° 85° Lead free part 12/1/04; v.1.3 ® –166 MHz AS7C33512PFD18A-166TQC AS7C33512PFD18A-166TQI 7C33512PFD18A Alliance Semiconductor AS7C33512PFD18A –133 MHz AS7C33512PFD18A-133TQC AS7C33512PFD18A-133TQI -166TQCN) –XXX TQ C ...
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... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33512PFD18A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C33512PFD18A Document Version: v.1.3 ...