as7c331mpfd18a Alliance Memory, Inc, as7c331mpfd18a Datasheet - Page 4

• Manufacturer Part Number: as7c331mpfd18a
• Description: 3.3v Pipelined Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Functional description
The AS7C331MPFD18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM)
device organized as 1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on
any given technology.
Fast cycle times of 6/7.5 ns with clock access times (t
enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address
strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated
burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK is
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but it is sampled on all subsequent clock edges. Address is incremented internally for the
next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO
input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the
device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes
may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low.
Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in double-
cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP are as follows:
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C331MPFD18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at
2.5V or 3.3V. These devices are available in a 100-pin TQFP package.
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
1 This parameter is sampled
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
2/10/05, v. 1.3
Parameter
Description
1
1
Symbol
C
C
I/O
IN
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
*
*
Test conditions
Alliance Semiconductor
V
V
Conditions
OUT
IN
= 0V
= 0V
CD
) of 3.4/3.8 ns enable 166, and 133 MHz bus frequencies. Three chip
®
Min
-
-
1–layer
4–layer
Max
5
7
Symbol
θ
θ
θ
JA
JA
JC
Unit
pF
pF
AS7C331MPFD18A
Typical
40
22
8
4 of 19
Units
°C/W
°C/W
°C/W