as7c331mpfd18a Alliance Memory, Inc, as7c331mpfd18a Datasheet - Page 11

• Manufacturer Part Number: as7c331mpfd18a
• Description: 3.3v Pipelined Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
*Outputs are disabled within two clk cycles after DSEL command
GWE, BWE
2/10/05, v. 1.3
CE0, CE2
Address
ADSP
ADSC
ADV
Dout
CLK
CE1
OE
t
Rising input
ADSPS
t
CSS
t
AS
A1
t
ADVS
t
t
t
Q(A1)
CSH
Read
t
AH
ADSPH
WS
t
LZOE
t
ADSCS
Suspend
Q(A1)
Read
t
t
t
WH
ADVH
OE
A2
Q(A1)
Q(A2)
Read
t
ADSCH
Falling input
t
Q(A 2Ý01 )
HZOE
Alliance Semiconductor
Burst
Read
t
t
CH
OH
Q(A2)
Q(A 2Ý10 )
LOAD NEW ADDRESS
Read
Burst
Q(A2Ý01)
t
CD
t
t
Q(A 2Ý10 )
CYC
Suspend
ADV inserts wait states
CL
Read
®
don’t care
Q(A 2Ý11 )
Q(A2Ý10)
Burst
Read
A3
Q(A3)
Read
Q(A2Ý11)
Q(A 3Ý01 )
Read
Burst
Undefined
Q(A3)
Q(A 3Ý10 )
Read
Burst
AS7C331MPFD18A
Q(A3Ý01)
Q(A 3Ý11 )
Burst
Read
Q(A3Ý10)
t
HZC
DSEL*
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