as7c331mntd32a Alliance Memory, Inc, as7c331mntd32a Datasheet - Page 4

• Manufacturer Part Number: as7c331mntd32a
• Manufacturer: Alliance Memory, Inc

Functional description
The AS7C331MNTD32A/36A family is a high performance CMOS 32 Mbit Synchronous Static Random Access Memory (SRAM)
organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 32Mb synchronous SRAM uses the No Turnaround Delay (NTD
that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for
valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or
read-modify-write operations.
NTD
flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
NTD
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined
mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W
pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including
burst, can be stalled using the CEN=1, the clock enable input.
The AS7C331MNTD32A/36A operates with a 3.3V ± 5% power supply for the device core (V
(V
TQFP Capacitance
*
TQFP thermal resistance
1 This parameter is sampled
Parameter
Input capacitance
I/O capacitance
Guaranteed not tested
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
DDQ
12/23/04, V 1.6
™
™
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP.
, write and read operations can be used in any order without producing dead bus cycles.
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle
Description
1
1
Symbol
C
C
I/O
IN
*
*
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
Test conditions
V
in
V
= V
in
= 0V
out
Conditions
= 0V
Alliance Semiconductor
Min
-
-
®
Max
5
7
™
1–layer
4–layer
) architecture, featuring an enhanced write operation
Unit
DD
pF
pF
). DQ circuits use a separate power supply
Symbol
θ
θ
θ
JA
JA
JC
AS7C331MNTD32A
AS7C331MNTD36A
Typical
40
22
8
P. 4 of 18
Units
°C/W
°C/W
°C/W