f25l16pa Elite Semiconductor Memory Technology Inc., f25l16pa Datasheet - Page 19

• Manufacturer Part Number: f25l16pa
• Description: 3v Only 16 Mbit Serial Flash Memory With Dual
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Write Status Register (WRSR)
The Write Status Register instruction writes new values to the
BP2, BP1, BP0, and BPL bits of the status register. CE must be
driven low before the command sequence of the WRSR
instruction is entered and driven high before the WRSR
instruction is executed. See Figure 16 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
status register, but cannot be reset from “1” to “0”.
Enter OTP Mode (ENSO)
The ENSO (B1H) instruction is for entering the additional 4K
bytes secured OTP mode. The additional 4K bytes secured OTP
sector is independent from main array, which may use to store
unique serial number for system identifier. User must unprotect
whole array (BP0=BP1=BP2=0), prior to any Program operation
in OTP sector. After entering the secured OTP mode, only the
secured OTP sector can be accessed and user can only follow
the Read or Program procedure with OTP address range
Elite Semiconductor Memory Technology Inc.
Figure 16: Enable Write Status Register (EWSR) or Write Enable (WREN) and Write Status Register (WRSR)
Figure 17: Enter OTP Mode (ENSO) Sequence
SCK
SO
CE
SI
MODE0
MODE3
MSB
0 1 2 3 4 5 6 7
50 or 06
HIGH IMPENANCE
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1,and BP2 bits in the status
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (V
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0; BP1 and BP2 bits
at the same time. See Table 4 for a summary description of WP
and BPL functions.
(address bits [A
cannot be updated again once it is lock down or has been
programmed. In secured OTP mode, WRSR command will
ignore the input data and lock down the secured OTP sector
(OTP_lock bit =1). To exit secured OTP mode, user must
execute WRDI command. RES can be used to verify the secured
OTP status as shown in Table 6.
CE pin at the end of the WRSR instruction, the bits in the status
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
MSB
01
23
–A
IH
7 6 5 4 3 2 1 0
12
) prior to the low-to-high transition of the
] must be “0”). The secured OTP data
REGISTER IN
Publication Date: Jul. 2009
Revision: 1.4
STATUS
F25L16PA
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