f25l16pa Elite Semiconductor Memory Technology Inc., f25l16pa Datasheet - Page 14

• Manufacturer Part Number: f25l16pa
• Description: 3v Only 16 Mbit Serial Flash Memory With Dual
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Auto Address Increment (AAI) WORD Program
The AAI program instruction allows multiple bytes of data to be
programmed without re-issuing the next sequential address
location. This feature decreases total programming time when
the multiple bytes or entire memory array is to be programmed.
An AAI program instruction pointing to a protected memory area
will be ignored. The selected address range must be in the
erased state (FFH) when initiating an AAI program instruction.
While within AAI WORD programming sequence, the only valid
instructions are AAI WORD program operation, RDSR, WRDI.
Users have three options to determine the completion of each
AAI WORD program cycle: hardware detection by reading the
SO; software detection by polling the BUSY in the software status
register or wait T
details.
Prior to any write operation, the Write Enable (WREN) instruction
must be executed. The AAI WORD program instruction is
initiated by executing an 8-bit command, ADH, followed by
address bits [A
is input sequentially. The data is input sequentially from MSB (bit
End of Write Detection
There are three methods to determine completion of a program
cycle during AAI WORD programming: hardware detection by
reading the SO, software detection by polling the BUSY bit in the
Hardware End of Write Detection
The Hardware End of Write Detection method eliminates the
overhead of polling the BUSY bit in the Software Status Register
during an AAI Word program operation. The 8-bit command, 70H,
configures the SO pin to indicate Flash busy status during AAI
WORD programming (refer to Figure 6). The 8-bit command, 70H,
must be executed prior to executing an AAI WORD program
instruction. Once an internal programming operation begins,
asserting CE will immediately drive the status of the internal flash
Elite Semiconductor Memory Technology Inc.
Figure 6: Enable SO as Hardware RY/ BY
during AAI Programming
23
-A
BP
0
. Refer to End of Write Detection section for
]. Following the addresses, two bytes of data
Figure 7: Disable SO as Hardware RY/ BY
7) to LSB (bit 0). The first byte of data (D0) will be programmed
into the initial address [A
data (D1) will be programmed into the initial address [A
A
instruction is executed. The user must check the busy status
before entering the next valid command. Once the device
indicates it is no longer busy, data for next two sequential
addresses may be programmed and so on. When the last desired
byte had been entered, check the busy status using the hardware
method or the RDSR instruction and execute the WRDI
instruction, to terminate AAI. User must check busy status after
WRDI to determine if the device is ready for any command.
Please refer to Figure 8 and Figure 9.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the device will
exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0)
and the AAI bit (AAI=0).
Software Status Register or wait T
Detection method is described in the section below.
status on the SO pin. A “0”
Indicates the device is busy; a “1” Indicates the device is ready
for the next instruction. De-asserting CE will return the SO pin
to tri-state. The 8-bit command, 80H, disables the SO pin to
output busy status during AAI WORD program operation and
return SO pin to output Software Status Register data during AAI
WORD programming (refer to Figure 7).
0
=1. CE must be driven high before the AAI WORD program
during AAI Programming
Publication Date: Jul. 2009
23
Revision: 1.4
-A
1
] with A
BP.
The Hardware End of Write
0
F25L16PA
=0; the second byte of
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23
-A
1
] with