gal22lv10z Lattice Semiconductor Corp., gal22lv10z Datasheet - Page 11
gal22lv10z
Manufacturer Part Number
gal22lv10z
Description
Low Voltage, Zero Power E2 Cmos Pld
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.GAL22LV10Z.pdf
(15 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
gal22lv10z-15QJ
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
All 3-state levels are measured at (Voh - 0.5) V
and (Vol + 0.5) V.
Output Load Conditions (see figure)
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
f
Active High
Active Low
Active High
Active Low
max with External Feedback 1/(
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
LOGIC
ARRAY
LOGIC
ARRAY
t
su +
f
t
max with No Feedback
su
t
h
270
270
270
270
270
R
1
REGISTER
REGISTER
CLK
CLK
220
220
220
220
220
R
2ns 10% – 90%
2
t
GND to 3.0V
t
su+
See Figure
co
1.5V
1.5V
t
co)
35pF
35pF
35pF
5pF
5pF
C
L
11
FROM OUTPUT (O/Q)
UNDER TEST
Specifications GAL22LV10Z
*C
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
L
f
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
max with Internal Feedback 1/(
LOGIC
ARRAY
R
2
+3.3V
GAL22LV10ZD
t
cf
t
pd
REGISTER
R
CLK
1
t
su+
C *
L
t
TEST POINT
cf)