74AUP1G240GM,115 NXP Semiconductors, 74AUP1G240GM,115 Datasheet - Page 3

• Manufacturer Part Number: 74AUP1G240GM,115
• Description: IC INVERTER 1-INPUT 6XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1G240GM,115

• Package / Case: 6-XSON (Micropak™), SOT-886
• Logic Type: Inverter
• Number Of Inputs: 1
• Number Of Circuits: 1
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: AUP
• Number Of Channels Per Chip: 1
• Polarity: Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 4 mA
• Input Bias Current (max): 0.5 uA
• Low Level Output Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 21.6 ns @ 1.1 V to 1.3 V or 12.3 ns @ 1.4 V to 1.6 V or 9.5 ns @ 1.65 V to 1.95 V or 7.1 ns @ 2.3 V to 2.7 V or 6.4 ns @ 3 V to 3.6 V
• Number Of Lines (input / Output): 1 / 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4379-2; 74AUP1G240GM-G; 74AUP1G240GM-G; 935279062115

NXP Semiconductors
6. Pinning information
Table 3.
7. Functional description
Table 4.
[1]
74AUP1G240
Product data sheet
Symbol
OE
A
GND
Y
n.c.
V
Input
OE
L
L
H
Fig 4.
CC
H = HIGH voltage level;
L = LOW voltage level;
X = Don’t care;
Z = high-impedance OFF-state.
GND
OE
A
Pin configuration
SOT353-1
Pin description
Function table
1
2
3
74AUP1G240
6.1 Pinning
6.2 Pin description
001aac525
Pin
TSSOP5
1
2
3
4
-
5
[1]
5
4
V
Y
CC
A
L
H
X
All information provided in this document is subject to legal disclaimers.
Fig 5.
XSON6
1
2
3
4
5
6
Rev. 2 — 13 September 2010
GND
OE
Pin configuration SOT886
A
Transparent top view
74AUP1G240
1
2
3
Description
output enable input
data input A
ground (0 V)
data output Y
not connected
supply voltage
001aac539
6
5
4
Low-power inverting buffer/line driver; 3-state
V
n.c.
Y
CC
Output
Y
H
L
Z
Fig 6.
GND
74AUP1G240
OE
Pin configuration SOT891,
SOT1115 and SOT1202
A
Transparent top view
74AUP1G240
1
2
3
© NXP B.V. 2010. All rights reserved.
001aaf549
6
5
4
V
n.c.
Y
CC
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