ht82j31a Holtek Semiconductor Inc., ht82j31a Datasheet - Page 29

• Manufacturer Part Number: ht82j31a
• Description: 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

SPI Configuration Options
Several configuration options exist for the SPI Interface
function which must be setup during device program-
ming. One option is to enable the operation of the
WCOL, write collision bit, in the SBCR register. Another
option exists to select the clock polarity of the SCK line.
A configuration option also exists to disable or enable
the operation of the CSEN bit in the SBCR register. If the
configuration option disables the CSEN bit then this bit
cannot be used to affect overall control of the SPI Inter-
face.
Rev. 1.00
Step 5. For write operations: write the data to the
Step 6. Check the WCOL bit, if set high then a
Step 7. Check the TRF bit or wait for an SBI serial bus
Step 8. Read data from the SBDR register.
Step 9. Clear TRF.
Step10. Goto step 5.
Slave Mode:
Step 1. The CKS bit has a don t care value in the
Step 2. Setup the M0 and M1 bits to 00 to select the
Step 3. Setup the CSEN bit and setup the MLS bit to
Step 4. Setup the SBEN bit in the SBCR control
Step 5. For write operations: write data to the SBCR
Step 6. Check the WCOL bit, if set high then a
Step 7. Check the TRF bit or wait for an SBI serial bus
Step 8. Read data from the SBDR register.
Step 9. Clear TRF
Step10. Goto step 5
data into the TXRX buffer. Then use the SCK
Goto to step6.For read operations: the data
in the TXRX buffer until all the data has been
collision error has occurred so return to step5.
If equal to zero then go to the following step.
interrupt.
this must be same as the Master device.
register to enable the SPI interface.
register, which will actually place the data into
the TXRX register, then wait for the master
For read operations: the data transferred in
at which point it will be latched into the SBDR
collision error has occurred so return to step5.
If equal to zero then go to the following step.
interrupt.
SBDR register, which will actually place the
and SCS lines to output the data.
transferred in on the SDI line will be stored
received at which point it will be latched into
the SBDR register.
slave mode.
Slave Mode. The CKS bit is don’t care.
choose if the data is MSB or LSB first,
clock and SCS signal. After this goto step 6.
on the SDI line will be stored in the TXRX
buffer until all the data has been received
register.
29
Error Detection
The WCOL bit in the SBCR register is provided to indi-
cate errors during data transfer. The bit is set by the Se-
rial Interface but must be cleared by the application
program. This bit indicates a data collision has occurred
which happens if a write to the SBDR register takes
place during a data transfer operation and will prevent
the write operation from continuing. The bit will be set
high by the Serial Interface but has to be cleared by the
user application program. The overall function of the
WCOL bit can be disabled or enabled by a configuration
option.
Programming Considerations
When the device is placed into the Power Down Mode
note that data reception and transmission will continue.
The TRF bit is used to generate an interrupt when the
data has been transferred or received.
Configuration Options
I/O Options
Oscillator Options
Watchdog Options
LVR Options
SPI Options
No.
10 CLRWDT instructions: one or two instructions
11 WDT Clock Source: Fsys/4 or WDT oscillator
12 LVR function: enable or disable
13 SPI_A: enable or disable
14 SPI_A WCOL bit: enable or disable
15 SPI_A CSEN bit: enable or disable
16
17 SPI_B: enable or disable
18 SPI_B WCOL bit: enable or disable
19 SPI_B CSEN bit: enable or disable
20
1
2
3
4
5
6
7
8
9
PA0~PA7: wake up enable or disable
PA0~PA7: pull-high enable or disable
PB0~PB3: pull-high enable or disable
PC1,PC2: pull-high enable or disable
PD1~PD3, PD4, PD7: pull-high enable or disable
PF0~PF2: pull-high enable or disable
PB2, PB3, PD4, PD7: CMOS or NMOS type
OSC type selection: RC or crystal
WDT: enable or disable
SPI_A SCK clock polarity: rising edge or falling
edge
SPI_B SCK clock polarity: rising edge or falling
edge
Options
September 19, 2007
HT82J31A