ht82j31a Holtek Semiconductor Inc., ht82j31a Datasheet - Page 19

• Manufacturer Part Number: ht82j31a
• Description: 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter overflow or transmission
or reception of SPI data occurs, their corresponding in-
terrupt will enforce a temporary suspension of the main
program allowing the microcontroller to direct attention
to their respective needs. Each device contains a single
external interrupt and several internal interrupts func-
tions. The external interrupt is controlled by the action of
the external interrupt pins, while the internal interrupts
are controlled by the Timer/Event Counter overflow and
the SPI interrupts.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by the two inter-
rupt control registers, which are located in the Data
Memory. By controlling the appropriate enable bits in
this register each individual interrupt can be enabled or
disabled. Also when an interrupt occurs, the corre-
sponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
Interrupt Operation
A Timer/Event Counter overflow, an SPI interrupt or an
active edge on the external interrupt pins will all gener-
ate an interrupt request by setting their corresponding
request flag, if their appropriate interrupt enable bit is
set. When this happens, the Program Counter, which
stores the address of the next instruction to be exe-
cuted, will be transferred onto the stack. The Program
Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction
from this interrupt vector. The instruction at this vector
will usually be a JMP statement which will jump to an-
other section of program which is known as the interrupt
service routine. Here is located the code to control the
appropriate interrupt. The interrupt service routine must
be terminated with a RETI statement, which retrieves
the original Program Counter address from the stack
and allows the microcontroller to continue with normal
execution at the point where the interrupt occurred.
Rev. 1.00
Bit No.
3, 6~7
0
1
2
4
5
EEI_A
EIF_A
Label
EMI
ETI
TF
Controls the master (global) interrupt (1= enable; 0= disable)
Controls the external interrupt (1= enabled; 0= disabled)
Controls the timer/event counter overflow interrupt (1= enabled; 0= disabled)
Unused bit, read as 0 .
External interrupt request flag (1= active; 0= inactive)
Internal timer/event counter overflow request flag (1= active; 0= inactive)
INTC0 Register
19
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the following dia-
gram with their order of priority.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
External Interrupt INT_A
Timer/Event Counter Overflow
Interrupt
SPI_A Interrupt
SPI_B Interrupt
External Interrupt INT_B
Function
Interrupt Source
Priority
September 19, 2007
1
2
3
4
5
HT82J31A
Vector
0010H
0014H
0018H
004H
008H