ht82v42 Holtek Semiconductor Inc., ht82v42 Datasheet - Page 14

• Manufacturer Part Number: ht82v42
• Description: Cis Analog Signal Processor
• Manufacturer: Holtek Semiconductor Inc.

Operating Modes
Operating Mode Timing Diagrams
The following diagrams show 4-bit multiplexed output data and DCLK, CDSCLK2 and input video requirements for
most common operations as shown in Table.
Rev. 1.00
Mode
ACYCNRLC
1
2
3
4
0
1
Monochrome/Colour
Line-by-Line
Fast Monochrome/
Colour Line-by-Line
Maximum speed
Monochrome/Colour
Line-by-Line
Slow Monochrome/
Colour Line-by-Line
Description
Internal no force mux
Auto-cycling, no force mux
Name
CDS
Yes
Yes
Yes
No
Colour Selection Description in Line-by-Line Mode
Sample
MSPS
MSPS
MSPS
MSPS
Max.
Rate
3.75
10
15
5
Only one input channel
at a time is
continuously sampled.
Identical to mode 1
Identical to mode 1
Identical to mode 1
HT82V42 Operating Modes
Sensor Interface
Input mux, offset and gain registers determined by internal register bits
INTM1, INTM0.
Input mux, offset and gain registers auto-cycled, RINP
BINP
Description
Mode 1 Operation
RINP
14
DCLK = 30MHz
DCLK: CDSCLK2
ratio is 6:1
DCLK = 30MHz
DCLK: CDSCLK2
ratio is 3:1
DCLK = 30MHz
DCLK: CDSCLK2
ratio is 2:1
DCLK = 30MHz
DCLK: CDSCLK2
ratio is 2n:1, n>=4
on RLC/ACYC pulse.
Requirement
Timing
Description
SetReg1 : 3F(h)
Identical to mode 1
plus SetReg3: bits 5:4
must be set to 0 (h)
CDS not possible
Identical to mode 1
Register Contents
With CDS
November 20, 2009
Register Contents
SetReg1:
2D(h)
Identical to
mode 1
SetReg1:
6D(h)
Identical to
mode 1
Without CDS
HT82V42
GINP