ht82v42 Holtek Semiconductor Inc., ht82v42 Datasheet
![no-image](/images/no-image-200.jpg)
ht82v42
Related parts for ht82v42
ht82v42 Summary of contents
Page 1
... Applications Flatbed document scanners Film scanners General Description The HT82V42 is a complete analog signal processor for CCD imaging applications. It features a 1-channel archi- tecture designed to sample and condition the outputs of tri-linear color CCD arrays. The channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA) and a high performance 16-bit A/D converter ...
Page 2
... Selectable analog output voltage for RLC or single-ended bias reference. This pin would VRLC/VBIAS AO typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-z. VIN AI Analog Input Note: AI=Analog Input; AO=Analog Output; AIO=Analog Inout DI=Digital Input; DO=Digital Output; P=Power Rev. 1.00 Description D10 D6 D2 D11 HT82V42 November 20, 2009 ...
Page 3
... Operating Temperature .............................. Digital supply power......................................3.0V~3.6V =3.3V, AGND=DGND=0V, Ta=25 C, DCLK=30MHz unless otherwise stated. Test Conditions Min. V Conditions DD 3.3V 0 Gain = 0dB; 3.3V PGA[7:0] = 54(hex) Gain = 0dB; 3.3V PGA[7:0] = 54(hex) 3.3V 3.3V Min Gain 3.3V Max Gain 1.90 0.90 0.9 3.3V 0.159 0.096 3.3V 0.35 0.35 3 HT82V42 Typ. Max. Unit V 0.27 P-P V 3.0 P 1.5 LSB 50 LSB 7 LSB rms 18 2.00 2.20 V 1.00 1. ...
Page 4
... Total Analog Supply Current Active (Signal Channel Mode) Digital Supply Current Active (DV ) DD1 Rev. 1.00 Test Conditions Min. V Conditions DD 3.3V 2.8 1.90 186/(278-PGA[7:0]) 6.50 0.65 0. =1mA DV -0 =1mA OL LINEBYLINE=1 DCLK=30MHz LINEBYLINE=1 DCLK=30MHz DCLK=30MHz 4 HT82V42 Typ. Max. Unit 3.0 3.10 V 2.00 2. bits 0.1 0.5 LSB 0.25 1.00 LSB 2.46 mV/step mV 315 +315 mV 8 bits V/V 8.00 8.40 V/V 0.68 0.75 V ...
Page 5
... Parameters are measured at 50% of the rising/falling edge. Rev. 1.00 Test Conditions Min. V Conditions DD DCLK=30MHz =3.3V, AGND=DGND=0V, Ta=25 C, DCLK=30MHz unless otherwise stated. Test Conditions V Conditions DD 3.3V Min. Typ. 33.3 16.6 16 HT82V42 Typ. Max. Unit 7 mA 300 A Min. Typ. Max. Unit 15 MSPS Max. Unit November 20, 2009 ...
Page 6
... AGND=DGND=0V, Ta=25 C, DCLK=30MHz unless otherwise stated. DD DD1 DD2 Symbol Parameter t Auto cycle setup time CYCSU t Auto cycle hold time ACYCH Rev. 1.00 Output Data Timing Min. Typ. Max. Auto Cycle Timing Min. Typ. Max HT82V42 Unit 16 ns Unit ns ns November 20, 2009 ...
Page 7
... SCK low to SDO = Register data SCRD t SCK low to SDO = ADC data SCRDZ Note: Parameters are measured at 50% of the rising/falling edge. Rev. 1.00 Serial Interface Timing Min. Typ. 37.6 18.8 18 HT82V42 Max. Unit November 20, 2009 ...
Page 8
... System Architecture Introduction A device block diagram showing the signal paths pres- ent is provided. The HT82V42 samples a single channel input V . The device then processes the sampled video IN signal with respect to the video reset level or an inter- nally/externally generated reference level for signal pro- cessing ...
Page 9
... Gain (V/V) = 186 / (278-PGA[7:0]) Gain (dB) = 20LOG PGA Gain Register Settings HT82V42 (186/(278-PGA[7:0])) 10 D0 Gain(V/V) Gain (dB) LSB 0 0. 3.50 10 November 20, 2009 ...
Page 10
... D2. Calculating Output for any Given Input The following equations describe the processing of the video and reset level signals through the HT82V42. The values of V1, V2 and V3 are often calculated in reverse order during device setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then ...
Page 11
... Output Data Formats (Mode Rev. 1.00 PGAFS[1: .................Eqn. 6 PGAFS[1: ..........................Eqn. 7 PGAFS[1: ..........................Eqn. 8 (INVOP = 0).....................................................Eqn. 9 (INVOP = 1)...................................................Eqn. 10 Output Data Formats (Mode 2) Output Format Output Pins 4+4+4+4-Bit OD3~OD0 (Nibble) Details of Output Data 11 HT82V42 Output A= d15~d12 B= d11~d8 C= d7~d4 D= d3~d0 November 20, 2009 ...
Page 12
... Table. Programmable CDSCLK2 Detect Circuit The CDSCLK2 input is used to determine the sampling point and frequency of the HT82V42. Under normal op- eration a pulse of 1 DCLK period should be applied to CDSCLK2 at the desired sampling frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on the first rising DCLK edge after CSDCLK2 has gone low ...
Page 13
... VRX is driven by a similar buffer, and also requires de- coupling. The output buffer from the RLCDAC also re- quires decoupling at pin VRLC/VBIAS. Power Supply The HT82V42 can run from a single 3.3V single supply. Power Management Power management for the device is performed via the Control Interface. The device can be powered on or off completely by clearing the EN bit low ...
Page 14
... SetReg3: bits 5:4 ratio is 3:1 must be set to 0 (h) DCLK = 30MHz Identical to mode 1 DCLK: CDSCLK2 CDS not possible ratio is 2:1 DCLK = 30MHz Identical to mode 1 DCLK: CDSCLK2 Identical to mode 1 ratio is 2n:1, n>=4 HT82V42 Operating Modes Mode 1 Operation 14 HT82V42 GINP Register Contents With CDS Without CDS SetReg1: 2D(h) Identical to mode 1 SetReg1: ...
Page 15
... Rev. 1.00 Mode 2 Operation Mode 3 Operation Mode 4 Operation 15 HT82V42 November 20, 2009 ...
Page 16
... RO[6] RO[5] RO[4] RO[3] GO[6] GO[5] GO[4] GO[3] BO[6] BO[5] BO[4] BO[3] RGBO[6] RGBO[5] RGBO[4] RGBO[3] RPGA[6] RPGA[5] RPGA[4] RPGA[3] GPGA[6] GPGA[5] GPGA[4] GPGA[3] BPGA[6] BPGA[5] BPGA[4] BPGA[3] 16 HT82V42 CDS EN INVOP 1 1 RLVC[2] RLVC[1] RLVC[0] 1 ACYCNRLC LINEBYLINE VDEL[1] VDEL[0] VSMPDET RO[2] RO[1] RO[0] GO[2] GO[1] GO[0] BO[2] BO[1] BO[0] ...
Page 17
... When this regis- ter is written, the reset function will be initiated immediately by an internal reset signal. If the DCLK exists, the internal reset signal will keep active for about 2 DCLK cycles. Otherwise, the device will keep in reset state all the time. 17 HT82V42 November 20, 2009 ...
Page 18
... Positive edge on the CDSCLK2 pin is detected and used to generate an internal timing pulse Internal clock monitor. 0: normal active, OD[3:0] output ADC data. 1: internal clock test mode. Pin ClkMotr=0 0 OD3 OD3 OD2 OD2 OD1 OD1 OD0 OD0 18 HT82V42 ClkMotr=1 INTVSMP Video sample clock ADC clock Reset sample clock November 20, 2009 ...
Page 19
... Blue PGA gain 5~0 BPGA RGB PGA gain 5~0 RGBPGA Application Circuits Recommended External Components Note: 1. All capacitors should be located as close to the HT82V42 as possible. 2. AGND and DGND should be connected as close to the HT82V42 as possible. Rev. 1.00 POR Description 80 Red offset value 80 Green offset value 80 Blue offset value ...
Page 20
... Package Information 20-pin SSOP (209mil) Outline Dimensions MO-150 Symbol Rev. 1.00 Dimensions in mm Min. Nom. 7.40 5.00 0.22 6.90 0.65 0.05 0.55 0. HT82V42 Max. 8.20 5.60 0.33 7.50 2.00 0.95 0.21 8 November 20, 2009 ...
Page 21
... TSSOP Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 1.05 0.05 0.95 0.22 0.13 6.4 6.3 4.3 0.65 0. HT82V42 Max. 1.2 0.15 1.05 0.17 6.6 6.5 4.5 0.75 0.1 8 November 20, 2009 ...
Page 22
... Key Slit Width T1 Space Between Flange T2 Reel Thickness TSSOP 20L Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.4 19.1 max. 22 November 20, 2009 HT82V42 ...
Page 23
... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm +0.3/-0.1 16.0 12.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 7.1 0.1 7.2 0.1 2.0 0.1 0.30 0.05 13.3 0.1 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.1/-0.0 1.5 4.0 0.1 2.0 0.1 6.8 0.1 6.9 0.1 1.6 0.1 0.30 0.05 13.3 0.1 23 November 20, 2009 HT82V42 ...
Page 24
... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 24 November 20, 2009 HT82V42 ...