ht82k96a Holtek Semiconductor Inc., ht82k96a Datasheet - Page 8

• Manufacturer Part Number: ht82k96a
• Description: Ht82k96a -- Usb Multimedia Keyboard Encoder 8-bit Mask Mcu
• Manufacturer: Holtek Semiconductor Inc.

At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return ad-
dresses are stored).
Data Memory - RAM for Bank 0
The data memory is designed with 190 8 bits. The
data memory is divided into two functional groups: spe-
cial function registers and general purpose data mem-
ory (160 8). Most are read/write, but some are read
only.
The special function registers include the indirect ad-
dressing registers (R0;00H, R1;02H), Bank register
(BP, 04H), Timer/Event Counter 0 (TMR0;0DH),
Timer/Event Counter 0 control register (TMR0C;0EH),
Timer/Event Counter 1 higher order byte register
(TMR1H;0FH), Timer/Event Counter 1 lower order byte
register (TMR1L;10H), Timer/Event Counter 1 control
register (TMR1C;11H), program counter lower-order
byte register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointer (TBLP;07H), table higher-order byte register
(TBLH;08H), status register (STATUS;0AH), interrupt
control register (INTC;0BH), Watchdog Timer option
setting register (WDTS;09H), I/O registers (PA;12H,
PB;14H, PC;16H, PD;18H), I/O control registers
(PAC;13H, PBC;15H, PCC;17H, PDC;19H). USB/PS2
status and control register (USC;1AH), USB endpoint
interrupt status register (USR;1BH), system clock con-
trol register (SCC;1CH). A/D converter status and con-
trol register (ADSC;1DH) and A/D converter result
register (ADR;1EH). The remaining space before the
20H is reserved for future expanded usage and reading
these locations will get 00H . The general purpose
data memory, addressed from 20H to BFH, is used for
data and control information under instruction com-
mands.
Rev. 1.50
8
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
memory pointer registers (MP0 or MP1).
CLR [m].i . They are also indirectly accessible through
Bank 0 RAM Mapping
HT82K96A
August 25, 2006