ht82k96a Holtek Semiconductor Inc., ht82k96a Datasheet - Page 11

• Manufacturer Part Number: ht82k96a
• Description: Ht82k96a -- Usb Multimedia Keyboard Encoder 8-bit Mask Mcu
• Manufacturer: Holtek Semiconductor Inc.

During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), USB interrupt request flag (USBF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-
able USB interrupt bit (EUI) and enable master interrupt
bit (EMI) constitute an interrupt control register (INTC)
which is located at 0BH in the data memory. EMI, EUI,
ET0I and ET1I are used to control the enabling/dis-
abling of interrupts. These bits prevent the requested in-
terrupt from being serviced. Once the interrupt request
flags (T0F, T1F, USBF) are set, they will remain in the
INTC register until the interrupts are serviced or cleared
by a software instruction.
It is recommended that a program does not use the
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Rev. 1.50
CALL subroutine within the interrupt subroutine. In-
No.
a
b
c
USB interrupt
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
Interrupt Source
Priority Vector
1
2
3
0CH
04H
08H
Watchdog Timer
11
Oscillator Configuration
There is an oscillator circuits in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31 s. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (sys-
tem clock divided by 4), determines the ROM code op-
tion. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by ROM code option. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
System Oscillator
HT82K96A
August 25, 2006