ht82k75rew Holtek Semiconductor Inc., ht82k75rew Datasheet - Page 63

• Manufacturer Part Number: ht82k75rew
• Description: Ht82m75rew/ht82k75rew 2.4ghz Transceiver 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

RF Transceiver Wake-up Operation
After entering into Power Saving Mode, the RF Transceiver could be waked up by the internal register trigger. One and
only one method should be used for wake-up operation.
Register Trigger Wake-up
User can wake the RF Transceiver up from STANDBY and DEEP_SLEEP modes by simply setting SREG0x22 [7:6] to
When the RF Transceiver is woken up by Register trigger, the following steps shall be executed to complete the opera-
tion:
Registers associated with Power Saving Operation:
Rev. 1.00
11 .
Configure clock recovery time
WAKECNT, used to calculate for recovery time of 32MHz clock of the RF Transceiver, should be set in advance. User
shall follow the following two steps to configure WAKECNT.
Wait the RF Transceiver issues a wake-up interrupt. The related wake-up interrupt flag is stored in SREG0x31 [6].
Turn on SPISYNC function by setting SREG0x26 [5] to 1.
Setting the LREG0x250 [4] to 1 to turn off the on-chip DC-DC converter.
Addr.
0x209
0x20A
0x20B
0x250
0x0D
0x22
0x26
0x31
0x35
0x36
Calculate the period of sleep clock
Set LREG0x20B [4] to 1 and then keep polling LREG0x20B [7] until the value becomes 1. After the value of
LREG0x20B [7] becomes 1, LREG0x20B [3:0], LREG0x20A, LREG0x209 form a 20-bit value C. Then the period
of the sleep clock (P
P
If the sleep clock frequency is higher than the expected value, user can configure LREG0x220 [4:0] to slow down
the clock rate. The new clock period P
P
Configure WAKECNT to set the recovery time of 32MHz clock to 180 s
Set WAKECNT, i.e. SREG0x36 [4:3] and SREG0x35 [6:0], to (1000*180) / P
sleep clock, P
sleepclock
sleepclock_new
File Name
SLPCAL_0
SLPCAL_1
SLPCAL_2
RFCTRL50
WAKECTL
RXFLUSH
GATECLK
SLPACK
ISRSTS
=
RFCTL
62 5
= P
.
16
sleepclock
xC
sleepclock_ori
(
SLPCALRD
SLPCAL15
IMMWAKE
ns
SLPCAL7
SLPACK
Bit 7
sleepclock
, is 10000ns. Set SREG0x36 [4:3] and SREG0x35 [6:0]} to 0x12.
)
Y
r
r
r
r
r
) can be calculated by the following equation:
2
WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 0000 0000
REGWAKE
SLPCAL14
SLPCAL6
WAKEIF
LREG0x220[4:0]
Bit 6
r
r
r
r
r
sleepclock_new
SLPCAL13
SPISYNC
SLPCAL5
(ns)
Bit 5
r
r
r
r
r
r
WAKECNT8 WAKECNT7
is obtained by the following equation:
SLPCALEN
SLPCAL12
SLPCAL4
DCPOC
Bit 4
63
r
r
r
r
SLPCAL11
SLPCAL19
SLPCAL3
DCOPC3
Bit 3
RXIF
r
r
r
HT82M75REW/HT82K75REW
SLPCAL10
SLPCAL18
SLPCAL2
DCOPC2
ENTXM
RFRST
Bit 2
PTX
sleepclock
r
r
SLPCAL17
. For example, the period of the
SLPCAL1
SLPCAL9
DCOPC1
Bit 1
r
r
r
r
r
SLPCAL16
RXFLUSH
SLPCAL0
SLPCAL8
DCOPC0
TXNIF
Bit 0
r
r
r
June 11, 2010
-0000 0000
0110 0000
0100 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Value on
POR