ox16pci954 ETC-unknow, ox16pci954 Datasheet - Page 55

• Manufacturer Part Number: ox16pci954
• Description: Integrated Quad Uart Interface
• Manufacturer: ETC-unknow

DSR[2]: INT#
logic 0
logic 1
This bit is activated (set low) on a rising edge of the ACK#
pin. It is de-activated (set high) after reading the DSR.
DSR[3]: ERR#
logic 0
logic 1
DSR[4]: SLCT
logic 0
logic 1
DSR[5]: PE
logic 0
logic 1
DSR[6]: ACK#
logic 0
logic 1
DSR[7]: nBUSY
logic 0
logic 1
9.3.3
DCR is located at offset 002h in the lower block. It is a
read-write register which controls the state of the peripheral
inputs and enables the peripheral interrupt. When reading
this register, bits 0 to 3 reflect the actual state of STB#,
AFD#, INIT# and SLIN# pins respectively. When in EPP
mode, the WRITE#, DATASTB# AND ADDRSTB# pins are
driven by the EPP controller, although writes to this register
will override the state of the respective lines.
DCR[0]: nSTB#
logic 0
logic 1
During an EPP address or data cycle the WRITE# pin is
driven by the EPP controller, otherwise it is inactive.
DCR[1]: nAFD#
logic 0
logic 1
During an EPP address or data cycle the DATASTB# pin is
driven by the EPP controller, otherwise it is inactive.
DCR[2]: INIT#
logic 0
logic 1
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
The PE input is low.
The PE input is high.
Device control register ‘DCR’
A parallel port interrupt is pending.
No parallel port interrupt is pending.
The ERR# input is low.
The ERR# input is high.
The SLCT input is low.
The SLCT input is high.
The ACK# input is low.
The ACK# input is high.
The BUSY input is high.
The BUSY input is low.
Set STB# output to high (inactive).
Set STB# output to low (active).
Set AFD# output to high (inactive).
Set AFD# output to low (active).
Set INIT# output to low (active).
Set INIT# output to high (inactive).
DCR[3]: nSLIN#
logic 0
logic 1
During an EPP address or data cycle the ADDRSTB# pin is
driven by the EPP controller, otherwise it is inactive.
DCR[4]: ACK Interrupt Enable
logic 0
logic 1
DCR[5]: DIR
logic 0
logic 1
This bit is overridden during an EPP address or data cycle,
when the direction of the port is controlled by the bus
access (read/write)
DCR[7:6]: Reserved
These bits are reserved and always set to “00”.
9.3.4
EPPA is located at offset 003h in lower block, and is only
used in EPP mode. A byte written to this register will be
transferred to the peripheral as an EPP address by the
hardware. A read from this register will transfer an address
from the peripheral under hardware control.
9.3.5
The EPPD registers are located at offset 004h-007h of the
lower block, and are only used in EPP mode. Data written
or read from these registers is transferred to/from the
peripheral under hardware control.
9.3.6
The Extended control register is located at offset 002h in
upper block. It is used to configure the operation of the
parallel port.
ECR[4:0]: Reserved
These bits are reserved and must always be set to
“00001”.
ECR[7:5]: Mode
These bits define the operational mode of the parallel port.
logic ‘000’
logic ‘001’
logic ‘010’
logic ‘011’
logic ‘100’
logic ‘101’
logic ‘110’
logic ‘111’
EPP address register ‘EPPA’
EPP data registers ‘EPPD1-4’
Extended control register ‘ECR’
Set SLIN# output to high (inactive).
Set SLIN# output to low (active).
ACK interrupt is disabled.
ACK interrupt is enabled.
PD port is output.
PD port is input.
SPP
PS2
Reserved
Reserved
EPP
Reserved
Reserved
Reserved
OX16PCI954
Page 55