zl2006 Intersil Corporation, zl2006 Datasheet - Page 18

• Manufacturer Part Number: zl2006
• Description: Adaptive Digital Dc-dc Controller With Drivers And Current Sharing
• Manufacturer: Intersil Corporation

Table 11. Soft Start Delay Settings
Note:
1. When the device is set to 0 ms or 1 ms delay, it will begin its
Table 12. Soft Start Ramp Settings
Note:
2. When the device is set to 0 ms ramp, it will attempt to ramp as fast
as the external load capacitance and loop settings will allow. It is
generally recommended to set the soft-start ramp to a value greater
than 500 µs to prevent inadvertent fault conditions due to excessive
inrush current.
If the desired soft start delay and ramp times are not
one of the values listed in Table 11 and Table 12, the
times can be set to a custom value by connecting a
resistor from the DLY0 or SS pin to SGND using the
appropriate resistor value from Table 13. The value of
this resistor is measured upon start-up or Restore and
will not change if the resistor is varied after power has
been applied to the ZL2006. See Figure 14 for typical
connections using resistors.
DLY1
Figure 14. DLY and SS Pin Resistor Connections
ramp up after the internal circuitry has initialized (approx. 2 ms).
OPEN
HIGH
LOW
OPEN
HIGH
LOW
SS
18
50 ms
0 ms
LOW
5 ms
1
100 ms
DLY0
Ramp Time
OPEN
10 ms
1 ms
0 ms
10 ms
5 ms
1
2
200 ms
20 ms
HIGH
2 ms
ZL2006
Table 13. DLY and SS Resistor Settings
Note: Do not connect a resistor to the DLY1 pin. This
pin is not utilized for setting soft-start delay times.
Connecting an external resistor to this pin may cause
conflicts with other device settings.
The soft start delay and ramp times can also be set to
custom values via the I
SS delay time is set to 0 ms, the device will begin its
ramp-up after the internal circuitry has initialized
(approx. 2 ms). When the soft-start ramp period is set
to 0 ms, the output will ramp up as quickly as the
output load capacitance and loop settings will allow. It
is generally recommended to set the soft-start ramp to a
value greater than 500 µs to prevent inadvertent fault
conditions due to excessive inrush current.
5.6 Power Good
The ZL2006 provides a Power Good (PG) signal that
indicates the output voltage is within a specified
tolerance of its target level and no fault condition
exists. By default, the PG pin will assert if the output is
within -10%/+15% of the target voltage. These limits
and the polarity of the pin may be changed via the
I
details.
A PG delay period is defined as the time from when all
conditions within the ZL2006 for asserting PG are met
to when the PG pin is actually asserted. This feature is
commonly used instead of using an external reset
controller to control external digital logic. By default,
the ZL2006 PG delay is set equal to the soft-start ramp
time setting. Therefore, if the soft-start ramp time is set
to 10 ms, the PG delay will be set to 10 ms. The PG
delay may be set independently of the soft-start ramp
using the I
AN33.
2
DLY or
100 ms
C/SMBus interface. See Application Note AN33 for
0 ms
10 ms
20 ms
30 ms
40 ms
50 ms
60 ms
70 ms
80 ms
90 ms
SS
2
2
C/SMBus as described in Application Note
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
R
10 kΩ
11 kΩ
DLY
R
SS
or
2
C/SMBus interface. When the
DLY or
110 ms
120 ms
130 ms
140 ms
150 ms
160 ms
170 ms
180 ms
190 ms
200 ms
SS
December 15, 2010
R
DLY
FN6850.1
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
56.2 kΩ
61.9 kΩ
68.1 kΩ
or R
SS