74AUP1G32GW,125 NXP Semiconductors, 74AUP1G32GW,125 Datasheet - Page 2

• Manufacturer Part Number: 74AUP1G32GW,125
• Description: IC 2-IN OR GATE LP 5-TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1G32GW,125

• Number Of Circuits: 1
• Package / Case: SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
• Logic Type: OR Gate
• Number Of Inputs: 2
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: AUP
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 19.1 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2563-2; 935279026125

NXP Semiconductors
3. Ordering information
Table 1.
4. Marking
Table 2.
[1]
5. Functional diagram
74AUP1G32
Product data sheet
Type number
74AUP1G32GW
74AUP1G32GM
74AUP1G32GF
74AUP1G32GN
74AUP1G32GS
Type number
74AUP1G32GW
74AUP1G32GM
74AUP1G32GF
74AUP1G32GN
74AUP1G32GS
Fig 1.
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
1
2
Logic symbol
Ordering information
Marking
B
A
Package
Temperature range Name
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
mna164
Y
4
All information provided in this document is subject to legal disclaimers.
Fig 2.
TSSOP5
XSON6
XSON6
XSON6
XSON6
Rev. 3 — 12 October 2010
1
2
IEC logic symbol
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
plastic extremely thin small outline package; no leads;
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads;
6 terminals; body 1 × 1 × 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 × 1.0 × 0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0 × 1.0 × 0.35 mm
≥1
Marking code
pG
pG
pG
pG
pG
mna165
4
[1]
Fig 3.
B
A
Low-power 2-input OR-gate
Logic diagram
74AUP1G32
© NXP B.V. 2010. All rights reserved.
Version
SOT353-1
SOT886
SOT891
SOT1115
SOT1202
mna166
2 of 20
Y