isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 4

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Pin Descriptions
Connection Notes
1. All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be
2. All analog output pins are “hard-wired” to internal output devices and should be left open if not used. V
3. When the signal input is single-ended, the other half of the unused differential input must be connected to a DC
Absolute Maximum Ratings
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7V
Logic and Analog Input Voltage Applied. . . . . . . . . . . . . . . 0 to VS
Logic and Analog Output Short Circuit Duration . . . . . . Indefinite
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . . .260°C
Ambient Temperature with Power Applied . . . . . . . . -55 to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Note: Stresses above those listed may cause permanent damage to the device. These are stress only ratings and functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied.
Pin(s)
10, 11
12, 15
13, 14
16
1
2
3
4
5
6
7
8
9
selected externally by reversing pin connections.
V
common-mode reference (usually VREF
OUT-
VREFOUT Common-Mode Reference Common-mode voltage reference output pin (+2.5V nominal).
should not be tied together as unnecessary power will be dissipated.
Symbol
ENSPI
TEST
GND
OUT
TCK
TMS
TDO
CAL
TDI
VS
CS
IN
Enable SPI Mode
Test Mode Select
Outputs (+ or -)
Supply Voltage
Auto-Calibrate
Inputs (+ or -)
Test Data Out
Chip Select
Test Data In
Test Clock
Test Pin
Ground
Name
OUT
, 2.5V).
Serial interface logic mode select pin (input). JTAG interface
mode only.
Serial interface logic clock pin (input). JTAG and SPI interface
modes.
Serial interface logic pin (input) for both JTAG and SPI opera-
tion modes.
Serial interface logic pin (output) for both JTAG and SPI opera-
tion modes. Input data valid on falling edge of TCK (JTAG), or
on rising edge of CS (SPI).
Chip select logic input pin. SPI data latch.
Digital pin (input). Commands an auto-calibration sequence on
a rising edge.
Enable SPI logic input pin. When high, causes serial port to run
in SPI mode.
Ground pin. Should normally be connected to the analog
ground plane.
Must be bypassed to GND with a 1µF capacitor.
Differential input pins, using two pins (e.g., IN+ and IN-). Plus or
minus components of V
Test pin. Connect to GND for proper circuit operation.
Differential output pins, using two pins (e.g., OUT+ and OUT-).
Complementary with respect to VREFOUT.
Differential V
Analog supply voltage pin (5V nominal). Should be bypassed to
GND with 1µF and .01µF capacitors.
4
OUT
= V
OUT+
IN
, where differential V
- V
Description
OUT
-.
ispPAC81 Data Sheet
IN
= V
IN+
OUT+
- V
IN-
and
.