isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 17

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states.
If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test
mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions
are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispPAC81 contains the required minimum instruction set as well as one from the optional instruction set.
In addition, there are several proprietary instructions that allow the device to be configured and verified. For
ispPAC81, the instruction word length is five bits. All ispPAC81 instructions available to users are shown in Table 5.
Table 5. ispPAC81 TAP Instructions
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC81.
The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard.
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC81 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode when-
ever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 5.
The EXTEST (External Test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the Boundary-Scan Register to be connected between TDI and TDO. Again, since
the ispPAC81 has no boundary-scan logic, the device is put in the BYPASS mode to ensure specification compati-
bility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros.
The optional IDCODE (Identification Code) instruction is incorporated in the ispPAC81 and leaves it in its functional
mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The
Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type
and version code (see Figure 7). Access to the Identification Register is immediately available, via a TAP data scan
operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction
is defined by Lattice as shown in Table 5.
EXTEST
ADDUSR
ABE
BBE
VERA
VERB
PRGA
PRGB
ENCAL
IDCODE
SAMPLE
BYPASS
Instruction
00000
00001
00010
00011
00100
00101
00110
00111
01100
01101
11110
11111
Code
External Test. Default to BYPASS.
Address User Data Register (A or B).
User A Bulk Erase.
User B Bulk Erase.
Verify User A Data Register.
Verify User B Data Register.
Program User A Data Register.
Program User B Data Register.
Enable Calibration Sequence.
Read Identification Data Register.
Sample/Preload. Default to BYPASS.
Bypass (Connect TDI to TDO).
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Description
ispPAC81 Data Sheet