isppac-powr6at6 Lattice Semiconductor Corp., isppac-powr6at6 Datasheet - Page 26

• Manufacturer Part Number: isppac-powr6at6
• Description: In-system Programmable Power Supply Monitoring And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
In-System Programming
The ispPAC-POWR6AT6 is an in-system programmable device. This is accomplished by integrating all E
ration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial
JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip,
in non-volatile E
instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
sists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inven-
tory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data
sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispPAC-POWR6AT6 device to prevent unauthorized
readout of the E
tional user bits in the device. This cell can only be erased by reprogramming the device, so the original configura-
tion cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are
discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
The Design Kit for the ispPAC-POWR1220AT8, a larger device that contains all the same functions as the ispPAC-
POWR6AT6, can be used to evaluate the ispPAC-POWR6AT6. Included in the basic ispPAC-POWR1220AT8
Design Kit is an engineering prototype board that can be connected to the parallel port of a PC using a Lattice
download cable. It demonstrates proper layout techniques for the ispPAC-POWR1220AT8 which also apply to the
ispPAC-POWR6AT6 and can be used in real time to check circuit operation as part of the design process. Input and
output connections are provided to aid in the evaluation of either device for a given application. (Figure 24).
Figure 24. Download from a PC
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispPAC-POWR6AT6 is facilitated via an IEEE 1149.1
test access port (TAP). It is used by the ispPAC-POWR6AT6 as a serial programming interface. A brief description
2
2
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-POWR6AT6
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the func-
PAC-Designer
Software
26
ispDOWNLOAD
2
Cable (6')
CMOS memory of the ispPAC-POWR6AT6. This con-
4
ispPAC-POWR
ispPAC-POWR6AT6 Data Sheet
Circuitry
System
1220AT8
Other
Device
2
configu-