isppac-powr6at6 Lattice Semiconductor Corp., isppac-powr6at6 Datasheet - Page 19

• Manufacturer Part Number: isppac-powr6at6
• Description: In-system Programmable Power Supply Monitoring And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 14. I
The ispPAC-POWR6AT6 provides 15 registers that can be accessed through its I
vide the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and from
the device. Table 4 provides a summary of these registers.
Table 4. I
I
Figure 15 shows bit assignments for the ispPAC-POWR6AT6 I
read only bits (cltlock_status.in[1:6]) that reflect the present trim status of individual trim output pins. When a closed
loop-trim controlled power supply's output reaches the value specified by its Profile 0 configuration setting, that trim
output's CLTLOCK_status bit is set to a “1”.
The I
PAC-Designer to operate in SMBus Alert mode, it is set to a “1” by device control logic to send an SMBus Alert.
Logic then waits for it to be acknowledged by a host I
Note: x = unknown, 0 = low, 1 = high, E= E
2
Register Address
C Closed-Loop Trim Register
2
C closed-loop trim register has one read/write bit (cltlock_status). When ispPAC-POWR6AT6 is configured in
0x0C
0x0D
0x0A
0x0B
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION
STEP 2: READ DATA FROM THAT REGISTER
2
C Control Registers
SDA
SDA
2
SCL
SCL
C Read Operation
START
START
Register Name
adc_value_high
adc_value_low
cltlock_status
UES_byte0
UES_byte1
UES_byte2
UES_byte3
A6
A6
trim1_trim
trim2_trim
trim3_trim
trim4_trim
trim5_trim
trim6_trim
1
1
adc_mux
reset
A5
A5
2
2
A4
A4
DEVICE ADDRESS (7 BITS)
DEVICE ADDRESS (7 BITS)
3
3
2
memory setting (UES string)
A3
A3
4
4
Read/Write
A2
A2
5
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A1
A1
W
R
R
R
R
R
R
6
6
A0
A0
7
7
R/W
R/W
8
8
Closed-loop trim status
*bit-6 is RW, all others R only
ADC D[3:0] and status
ADC D[11:4]
ADC Attenuator and MUX[3:0]
UES[7:0]
UES[15:8]
UES[23:16]
UES[31:24]
Resets device on write
Trim DAC 1 [7:0]
Trim DAC 2 [7:0]
Trim DAC 3 [7:0]
Trim DAC 4 [7:0]
Trim DAC 5 [7:0]
Trim DAC 6 [7:0]
2
C processor (when it is addresses the register), completing
ACK
ACK
19
9
9
R7
D7
1
1
2
C closed-loop trim status register. There are six
Description
R6
D6
2
2
REGISTER ADDRESS (8 BITS)
R5
D5
3
3
READ DATA (8 BITS)
ispPAC-POWR6AT6 Data Sheet
R4
D4
4
4
R3
D3
5
5
2
C interface. These registers pro-
R2
D2
6
6
Note: Shaded Bits Asserted by Slave
R1
D1
7
7
R0
D0
8
8
OPTIONAL
Value on POR, RESET
ACK
ACK
9
9
EEEE EEEE
EEEE EEEE
EEEE EEEE
EEEE EEEE
1100 0000
0000 1110
0000 0000
1110 1000
1111 1111
1000 0000
1000 0000
1000 0000
1000 0000
1000 0000
1000 0000
STOP
STOP